Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Buffer, driver TSSOP 20

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SCBS134K − SEPTEMBER 1992 − REVISED JANUARY 2004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Supports Mixed-Mode Signal Operation

(5-V Input and Output Voltages With 3.3-V

)

D Supports Unregulated Battery Operation

Down To 2.7 V

D Typical V

OLP

(Output Ground Bounce)

<0.8 V at V

= 3.3 V, T

= 25°C

D I

off

and Power-Up 3-State Support Hot

Insertion

D Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

D ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

− 1000-V Charged-Device Model (C101)

description/ordering information

This octal buffer and line driver is designed specifically for low-voltage (3.3-V) V

operation, but with the

capability to provide a TTL interface to a 5-V system environment.

The SN74LVT240A is organized as two 4-bit buffer/line drivers with separate output-enable (OE

) inputs. When

is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the

high-impedance state.

When V

is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.

However, to ensure the high-impedance state above 1.5 V, OE

should be tied to V

through a pullup resistor;

the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for hot-insertion applications using I

off

and power-up 3-state. The I

off

circuitry

disables the outputs, preventing damaging current backflow through the device when it is powered down. The

power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,

which prevents driver conflict.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

SOIC − DW

Tube SN74LVT240ADW

LVT240A

SOIC − DW

Tape and reel SN74LVT240ADWR

LVT240A

SOP − NS Tape and reel SN74LVT240ANSR LVT240A

−40°C to 85°C

SSOP − DB Tape and reel SN74LVT240ADBR LX240A

−40 C to 85 C

TSSOP − PW

Tube SN74LVT240APW

LX240A

TSSOP − PW

Tape and reel SN74LVT240APWR

LX240A

TVSOP − DGV Tape and reel SN74LVT240ADGVR LX240A

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines

are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

DB, DGV, DW, NS, OR PW PACKAGE

(TOP VIEW)

1OE

1A1

2Y4

1A2

2Y3

1A3

2Y2

1A4

2Y1

GND

2OE

1Y1

2A4

1Y2

2A3

1Y3

2A2

1Y4

2A1

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Summary of content (15 pages)

PAGE 1
SCBS134K − SEPTEMBER 1992 − REVISED JANUARY 2004 D Supports Mixed-Mode Signal Operation D D D D D DB, DGV, DW, NS, OR PW PACKAGE (TOP VIEW) (5-V Input and Output Voltages With 3.3-V VCC ) Supports Unregulated Battery Operation Down To 2.7 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.
PAGE 2
SCBS134K − SEPTEMBER 1992 − REVISED JANUARY 2004 FUNCTION TABLE (each 4-bit buffer) INPUTS OE A OUTPUT Y L H L L L H H X Z logic diagram (positive logic) 1OE 1A1 1A2 1A3 1A4 1 2OE 2 18 4 16 6 14 8 12 1Y1 2A1 1Y2 2A2 1Y3 2A3 1Y4 2A4 19 11 9 13 7 15 5 17 3 2Y1 2Y2 2Y3 2Y4 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . .
PAGE 3
SCBS134K − SEPTEMBER 1992 − REVISED JANUARY 2004 recommended operating conditions (see Note 4) MIN MAX 2.7 3.6 UNIT VCC VIH Supply voltage VIL VI Low-level input voltage Input voltage 5.5 V IOH IOL High-level output current −32 mA ∆t/∆v Input transition rise or fall rate ∆t/∆VCC TA Power-up ramp rate 200 Operating free-air temperature −40 High-level input voltage 2 V 0.
PAGE 4
SCBS134K − SEPTEMBER 1992 − REVISED JANUARY 2004 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1) FROM (INPUT) TO (OUTPUT) tPLH tPHL A Y tPZH tPZL OE Y tPHZ tPLZ OE Y PARAMETER † All typical values are at VCC = 3.3 V, TA = 25°C. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 VCC = 3.3 V ± 0.3 V VCC = 2.7 V MIN TYP† MAX 1.1 2.
PAGE 5
SCBS134K − SEPTEMBER 1992 − REVISED JANUARY 2004 PARAMETER MEASUREMENT INFORMATION 500 Ω From Output Under Test 6V Open S1 GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 6V GND 2.7 V LOAD CIRCUIT Timing Input 1.5 V 0V tw tsu 2.7 V Input 1.5 V th 2.7 V 1.5 V Data Input 1.5 V 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V 2.7 V 1.
PAGE 6
PACKAGE OPTION ADDENDUM www.ti.
PAGE 7
PACKAGE OPTION ADDENDUM www.ti.com 11-Nov-2009 package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp.
PAGE 8
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74LVT240ADBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 SN74LVT240ADWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 SN74LVT240ANSR SO NS 20 2000 330.0 24.4 8.2 13.0 2.5 12.0 24.
PAGE 9
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVT240ADBR SN74LVT240ADWR SSOP DB 20 2000 367.0 367.0 38.0 SOIC DW 20 2000 367.0 367.0 45.0 SN74LVT240ANSR SO NS 20 2000 367.0 367.0 45.0 SN74LVT240APWR TSSOP PW 20 2000 367.0 367.0 38.
PAGE 10
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PAGE 14
MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
PAGE 15
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.