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SN54LVT8996, SN74LVT8996

3.3-V 10-BIT ADDRESSABLE SCAN PORTS

MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS

SCBS686A – APRIL 1997 – REVISED DECEMBER 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Members of the Texas Instruments (TI)

Broad Family of Testability Products

Supporting IEEE Std 1149.1-1990 (JTAG)

Test Access Port (TAP) and Boundary-Scan

Architecture

Extend Scan Access From Board Level to

Higher Levels of System Integration

Promote Reuse of Lower-Level

(Chip/Board) Tests in System Environment

While Powered at 3.3 V, Both the Primary

and Secondary TAPs Are Fully 5-V Tolerant

for Interfacing to 5-V and/or 3.3-V Masters

and Targets

Switch-Based Architecture Allows Direct

Connect of Primary TAP to Secondary TAP

Primary TAP Is Multidrop for Minimal Use of

Backplane Wiring Channels

Shadow Protocols Can Occur in Any of

Test-Logic-Reset, Run-Test/Idle, Pause-DR,

and Pause-IR TAP States to Provide for

Board-to-Board Test and Built-In Self-Test

Simple Addressing (Shadow) Protocol Is

Received/Acknowledged on Primary TAP

10-Bit Address Space Provides for up to

1021 User-Specified Board Addresses

Bypass (BYP) Pin Forces

Primary-to-Secondary Connection Without

Use of Shadow Protocols

Connect (CON) Pin Provides Indication of

Primary-to-Secondary Connection

High-Drive Outputs (–32-mA I

, 64-mA I

)

Support Backplane Interface at Primary and

High Fanout at Secondary

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

– 1000-V Charged-Device Model (C101)

Package Options Include Plastic

Small-Outline (DW) and Thin Shrink

Small-Outline (PW) Packages, Ceramic

Chip Carriers (FK), and Ceramic DIPs (JT)

SN54LVT8996 ...JT PACKAGE

SN74LVT8996 . . . DW OR PW PACKAGE

(TOP VIEW)

BYP

GND

PTDO

PTCK

PTMS

PTDI

PTRST

CON

STDI

STCK

STMS

STDO

STRST

432128

12 13 14 15 16

CON

STDI

STCK

BYP

GND

PTDO

PTCK

SN54LVT8996 . . . FK PACKAGE

(TOP VIEW)

STRST

STDO

PTDI

PTRST

PTMS

STMS

27 26

NC – No internal connection

description

The ’LVT8996 10-bit addressable scan ports (ASP) are members of the Texas Instruments SCOPE testability

integrated-circuit family. This family of devices supports IEEE Std 1149.1-1990 boundary scan to facilitate

testing of complex circuit assemblies. Unlike most SCOPE devices, the ASP is not a boundary-scannable

device, rather, it applies TI’s addressable-shadow-port technology to the IEEE Std 1149.1-1990 (JTAG) test

access port (TAP) to extend scan access beyond the board level.

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SCOPE and TI are trademarks of Texas Instruments Incorporated.

Summary of content (48 pages)

PAGE 1
SN54LVT8996, SN74LVT8996 3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.
PAGE 2
SN54LVT8996, SN74LVT8996 3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS SCBS686A – APRIL 1997 – REVISED DECEMBER 1999 description (continued) These devices are functionally equivalent to the ’ABT8996 ASPs. Additionally, they are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to interface to 5-V masters and/or targets.
PAGE 3
SN54LVT8996, SN74LVT8996 3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS SCBS686A – APRIL 1997 – REVISED DECEMBER 1999 description (continued) Whether the connected status is achieved by use of shadow protocol or by use of BYP, this status is indicated by a low level at the connect (CON) output. Likewise, when the secondary TAP is disconnected from the primary TAP, the CON output is high.
PAGE 4
SN54LVT8996, SN74LVT8996 3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS SCBS686A – APRIL 1997 – REVISED DECEMBER 1999 functional block diagram PTCK PTRST PTMS 9 16 VCC 12 13 VCC STCK STRST S 10 1D VCC 15 STMS C1 PTDI STDI 14 11 VCC 17 VCC BYP STDO 8 PTDO 6 Shadow-Protocol Receive A9–A0 VCC 20–24, 1–5 Connect Control 18 Shadow-Protocol Transmit Pin numbers shown are for the DW, JT, and PW packages.
PAGE 5
SN54LVT8996, SN74LVT8996 3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS SCBS686A – APRIL 1997 – REVISED DECEMBER 1999 Terminal Functions TERMINAL NAME DESCRIPTION A9–A0 Address inputs. The ASP compares addresses received via shadow protocol against the value at A9–A0 to determine address match. The bit order is from most significant to least significant.
PAGE 6
SN54LVT8996, SN74LVT8996 3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS SCBS686A – APRIL 1997 – REVISED DECEMBER 1999 application information In application, the ASP is used at each of several (serially-chained) groups of IEEE Std 1149.1-compliant devices. The ASP for each such group is assigned an address (via inputs A9–A0) that is unique from that assigned to ASPs for the remaining groups.
PAGE 7
SN54LVT8996, SN74LVT8996 3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS SCBS686A – APRIL 1997 – REVISED DECEMBER 1999 architecture Conceptually, the ASP can be viewed as a bank of switches that can connect or isolate a module-level TAP to/from a higher-level (e.g., module-to-module) TAP. This is shown in Figure 2. The state of the switches (open versus closed) is based on shadow protocols, which are received on PTDI and are synchronous to PTCK.
PAGE 8
SN54LVT8996, SN74LVT8996 3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS SCBS686A – APRIL 1997 – REVISED DECEMBER 1999 shadow protocol Addressing of an ASP in system is accomplished by shadow protocols, which are received at PTDI synchronously to PTCK. Shadow protocols can occur only in the following stable TAP states: Test-Logic-Reset, Run-Test/Idle, Pause-DR, and Pause-IR.
PAGE 9
SN54LVT8996, SN74LVT8996 3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS SCBS686A – APRIL 1997 – REVISED DECEMBER 1999 select protocol The select protocol is the ASP’s means of receiving (at PTDI) address information from an IEEE Std 1149.1 bus master. It follows the ISDDDDDDDDDDSI sequence described previously. A 10-bit address value is decoded from the received data-one and/or data-zero bit pairs.
PAGE 10
SN54LVT8996, SN74LVT8996 3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS SCBS686A – APRIL 1997 – REVISED DECEMBER 1999 short address In all cases, receipt of an address shorter than ten bits produces protocol result HARD ERROR and the ASP assumes OFF status.
PAGE 11
SN54LVT8996, SN74LVT8996 3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS SCBS686A – APRIL 1997 – REVISED DECEMBER 1999 Test-Logic-Reset The ASP TAP-state monitor powers up in the Test-Logic-Reset state. Alternatively, the ASP can be forced asynchronously to this state by assertion of its PTRST input. In the stable Test-Logic-Reset state, the ASP is enabled to receive and respond to shadow protocols. The ASP does not recognize the TSA in this state.
PAGE 12
SN54LVT8996, SN74LVT8996 3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS SCBS686A – APRIL 1997 – REVISED DECEMBER 1999 Update-DR The ASP is not enabled to receive and respond to shadow protocols in the Update-DR state. For a target device, if the current instruction calls for the selected data register to be updated with current data, such update occurs on the falling edge of TCK, following entry to the Update-DR state.
PAGE 13
SN54LVT8996, SN74LVT8996 3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS SCBS686A – APRIL 1997 – REVISED DECEMBER 1999 address matching Connect status of the ASP is computed by a match of the address received in the last valid shadow protocol against that at the address inputs (A9–A0) as well as against the three dedicated addresses that are internal to the ASP (DSA, RSA, and TSA). The address map is shown in Table 2. Table 2.
PAGE 14
SN54LVT8996, SN74LVT8996 3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS SCBS686A – APRIL 1997 – REVISED DECEMBER 1999 test synchronization address The test synchronization address (TSA) is one of the three internally dedicated addresses that are recognized globally.
PAGE 15
SN54LVT8996, SN74LVT8996 3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.
PAGE 16
SN54LVT8996, SN74LVT8996 3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.
PAGE 17
SN54LVT8996, SN74LVT8996 3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS SCBS686A – APRIL 1997 – REVISED DECEMBER 1999 PTCK Don’t Care A9–A0 Don’t Care BYP PTDI Idle Select NMAP Select Idle Don’t Care PTMS Don’t Care PTRST Don’t Care STDI CON PTDO PTDO = STDI STCK STDO NMAP STMS STMS = PTMS STMS = STMS0 STRST Select Protocol OFF Figure 8.
PAGE 18
SN54LVT8996, SN74LVT8996 3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS SCBS686A – APRIL 1997 – REVISED DECEMBER 1999 PTCK Don’t Care A9–A0 Don’t Care BYP PTDI Idle Select NMAP Select Idle Don’t Care PTMS Don’t Care PTRST Don’t Care STDI CON PTDO STCK STDO STMS = STMS0 STMS STRST Select Protocol OFF Figure 9.
PAGE 19
SN54LVT8996, SN74LVT8996 3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS SCBS686A – APRIL 1997 – REVISED DECEMBER 1999 PTCK Don’t Care A9–A0 BYP PTDI Idle Select DSAP Select Idle Don’t Care PTMS Don’t Care PTRST Don’t Care STDI CON PTDO PTDO = STDI STCK STDO STMS DSAP STMS = PTMS STMS = STMS0 STRST Select Protocol OFF Figure 10.
PAGE 20
SN54LVT8996, SN74LVT8996 3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS SCBS686A – APRIL 1997 – REVISED DECEMBER 1999 PTCK Don’t Care A9–A0 BYP PTDI Idle Select DSAP Select Idle Don’t Care PTMS Don’t Care PTRST Don’t Care STDI CON PTDO STCK STDO STMS = STMS0 STMS STRST Select Protocol OFF Figure 11.
PAGE 21
SN54LVT8996, SN74LVT8996 3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS SCBS686A – APRIL 1997 – REVISED DECEMBER 1999 PTCK Don’t Care A9–A0 BYP PTDI Idle Select RSAP Select Idle Don’t Care PTMS Don’t Care PTRST Don’t Care STDI CON PTDO PTDO = STDI STCK STDO RSAP STMS STMS = PTMS STRST Select Protocol RESET Figure 12.
PAGE 22
SN54LVT8996, SN74LVT8996 3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS SCBS686A – APRIL 1997 – REVISED DECEMBER 1999 PTCK Don’t Care A9–A0 BYP PTDI Idle Select RSAP Select Idle Don’t Care PTMS Don’t Care PTRST Don’t Care STDI CON PTDO STCK STDO STMS STMS = STMS0 STRST Select Protocol RESET Figure 13.
PAGE 23
SN54LVT8996, SN74LVT8996 3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS SCBS686A – APRIL 1997 – REVISED DECEMBER 1999 PTCK Don’t Care A9–A0 BYP PTDI Idle Select TSAP Select Idle Don’t Care PTMS Don’t Care PTRST Don’t Care STDI CON PTDO PTDO = STDI STCK STDO STMS TSAP STDO = PTDI STMS = PTMS STMS = PTMS STRST Select Protocol MULTICAST Figure 14.
PAGE 24
SN54LVT8996, SN74LVT8996 3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS SCBS686A – APRIL 1997 – REVISED DECEMBER 1999 PTCK Don’t Care A9–A0 BYP PTDI Idle Select TSAP Select Idle Don’t Care PTMS Don’t Care PTRST Don’t Care STDI CON PTDO STCK STDO STMS STDO = PTDI STMS = STMS0 STMS = PTMS STRST Select Protocol MULTICAST Figure 15.
PAGE 25
SN54LVT8996, SN74LVT8996 3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.
PAGE 26
SN54LVT8996, SN74LVT8996 3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.
PAGE 27
SN54LVT8996, SN74LVT8996 3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.
PAGE 28
SN54LVT8996, SN74LVT8996 3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS SCBS686A – APRIL 1997 – REVISED DECEMBER 1999 protocol-bypass timing PTCK Don’t Care A9–A0 BYP PTDI Don’t Care PTMS Don’t Care PTRST Don’t Care STDI CON PTDO = STDI PTDO STCK STDO STDO = PTDI STMS STMS = PTMS STRST ON BYP ON Figure 19.
PAGE 29
SN54LVT8996, SN74LVT8996 3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS SCBS686A – APRIL 1997 – REVISED DECEMBER 1999 PTCK Don’t Care A9–A0 BYP PTDI Don’t Care PTMS Don’t Care PTRST Don’t Care STDI CON PTDO = STDI PTDO STCK STDO STDO = PTDI STMS STMS = STMS0 STMS = PTMS STMS = STMS0 STRST OFF BYP OFF Figure 20.
PAGE 30
SN54LVT8996, SN74LVT8996 3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS SCBS686A – APRIL 1997 – REVISED DECEMBER 1999 asynchronous reset timing PTCK Don’t Care A9–A0 BYP PTDI Don’t Care PTMS Don’t Care PTRST Don’t Care STDI CON PTDO PTDO = STDI STCK STDO STDO = PTDI STMS STMS = PTMS STRST ON TRST RESET Figure 21.
PAGE 31
SN54LVT8996, SN74LVT8996 3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS SCBS686A – APRIL 1997 – REVISED DECEMBER 1999 PTCK Don’t Care A9–A0 BYP PTDI Don’t Care PTMS Don’t Care PTRST Don’t Care STDI CON PTDO STCK STDO STMS STMS = STMS0 STRST OFF TRST RESET Figure 22.
PAGE 32
SN54LVT8996, SN74LVT8996 3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS SCBS686A – APRIL 1997 – REVISED DECEMBER 1999 PTCK Don’t Care A9–A0 BYP PTDI Don’t Care PTMS Don’t Care PTRST Don’t Care STDI CON PTDO = STDI PTDO STCK STDO = PTDI STDO STMS = PTMS STMS STMS = PTMS STRST BYP BYP/TRST BYP Figure 23.
PAGE 33
SN54LVT8996, SN74LVT8996 3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS SCBS686A – APRIL 1997 – REVISED DECEMBER 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 34
SN54LVT8996, SN74LVT8996 3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS SCBS686A – APRIL 1997 – REVISED DECEMBER 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK SN54LVT8996 TYP† MAX TEST CONDITIONS MIN VCC = 2.7 V, II = –18 mA VCC = 2.7 V to 3.6 V, IOH = –100 µA VCC = 2.7 V, VOH VCC = 3 V SN74LVT8996 TYP† MAX MIN –1.2 VCC–0.2 2.4 IOH = – 8 mA IOH = –24 mA –1.2 VCC–0.
PAGE 35
SN54LVT8996, SN74LVT8996 3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS SCBS686A – APRIL 1997 – REVISED DECEMBER 1999 timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 24) SN54LVT8996 MIN fclock l k tw Clock frequency Pulse duration VCC = 2.7 V VCC = 3.3 V ± 0.
PAGE 36
SN54LVT8996, SN74LVT8996 3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS SCBS686A – APRIL 1997 – REVISED DECEMBER 1999 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 24) SN54LVT8996 PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 3.3 V ± 0.3 V MIN MAX VCC = 2.7 V MIN MAX fmax tPLH PTCK 25 BYP↑ 1 8.7 1 10 tPHL tPLH BYP↓ 1 10 1 11.6 2.5 12.6 2.5 15.
PAGE 37
SN54LVT8996, SN74LVT8996 3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS SCBS686A – APRIL 1997 – REVISED DECEMBER 1999 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) (see Figure 24) SN54LVT8996 PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 3.3 V ± 0.3 V MIN tPZH† VCC = 2.7 V MAX MIN 1.5 9.5 1.5 11.6 1.5 10.7 1.5 12.7 1.5 8.6 1.5 10.2 1.5 9.7 1.
PAGE 38
SN54LVT8996, SN74LVT8996 3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS SCBS686A – APRIL 1997 – REVISED DECEMBER 1999 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 24) SN74LVT8996 PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 3.3 V ± 0.3 V MIN MAX VCC = 2.7 V MIN MAX fmax tPLH PTCK 25 BYP↑ 1 8.2 1 9.4 tPHL tPLH BYP↓ 1 9.8 1 11.4 2.5 12 2.5 14.
PAGE 39
SN54LVT8996, SN74LVT8996 3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS SCBS686A – APRIL 1997 – REVISED DECEMBER 1999 switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) (see Figure 24) SN74LVT8996 PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 3.3 V ± 0.
PAGE 40
SN54LVT8996, SN74LVT8996 3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 (JTAG) TAP TRANSCEIVERS SCBS686A – APRIL 1997 – REVISED DECEMBER 1999 PARAMETER MEASUREMENT INFORMATION 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 6V GND 2.7 V LOAD CIRCUIT 1.5 V Timing Input 0V tw tsu 2.7 V 1.5 V Input 1.5 V th 2.7 V 1.5 V Data Input 1.
PAGE 41
PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 24-Jan-2013 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74LVT8996DWR Package Package Pins Type Drawing SOIC DW 24 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 24.4 Pack Materials-Page 1 10.75 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 15.7 2.7 12.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVT8996DWR SOIC DW 24 2000 367.0 367.0 45.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.