Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Buffer, driver SOIC 14

 

    

  

SCBS703I − AUGUST 1997 − REVISED OCTOBER 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Support Mixed-Mode Signal Operation (5-V

Input and Output Voltages With 3.3-V V

)

D Support Unregulated Battery Operation

Down to 2.7 V

D Typical V

OLP

(Output Ground Bounce)

<0.8 V at V

= 3.3 V, T

= 25°C

D I

off

and Power-Up 3-State Support Hot

Insertion

D Bus Hold on Data Inputs Eliminates the

Need for External Pullup/Pulldown

Resistors

D Latch-Up Performance Exceeds 500 mA Per

JESD 17

D ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

SN54LVTH125 ...J OR W PACKAGE

SN74LVTH125 . . . D, DB, DGV, NS,

OR PW PACKAGE

(TOP VIEW)

SN54LVTH125 . . . FK PACKAGE

(TOP VIEW)

1OE

2OE

GND

4OE

3OE

3212019

910111213

3OE

2OE

1OE

4OE

GND

NC − No internal connection

SN74LVTH125 . . . RGY PACKAGE

(TOP VIEW)

114

4OE

3OE

2OE

1OE

GND

description/ordering information

These bus buffers are designed specifically for low-voltage (3.3-V) V

operation, but with the capability to

provide a TTL interface to a 5-V system environment.

The ’LVTH125 devices feature independent line drivers with 3-state outputs. Each output is in the

high-impedance state when the associated output-enable (OE

) input is high.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

QFN − RGY Tape and reel SN74LVTH125RGYR LXH125

SOIC − D

Tube SN74LVTH125D

LVTH125

SOIC − D

Tape and reel SN74LVTH125DR

LVTH125

−40°C to 85°C

SOP − NS Tape and reel SN74LVTH125NSR LVTH125

−40°C to 85°C

SSOP − DB Tape and reel SN74LVTH125DBR LXH125

TSSOP − PW

Tube SN74LVTH125PW

LXH125

TSSOP − PW

Tape and reel SN74LVTH125PWR

LXH125

TVSOP − DGV Tape and reel SN74LVTH125DGVR LXH125

CDIP − J Tube SNJ54LVTH125J SNJ54LVTH125J

−55°C to 125°C

CFP − W Tube SNJ54LVTH125W SNJ54LVTH125W

−55 C to 125 C

LCCC − FK Tube SNJ54LVTH125FK SNJ54LVTH125FK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Summary of content (22 pages)

PAGE 1
SCBS703I − AUGUST 1997 − REVISED OCTOBER 2003 D Support Mixed-Mode Signal Operation (5-V 13 3 12 4 11 5 10 6 9 7 8 VCC 4OE 4A 4Y 3OE 3A 3Y 1A 1Y 2OE 2A 2Y 14 1A 1OE NC VCC 4OE 1 2 13 4OE 3 12 4A 4 11 4Y 5 10 3OE 9 3A 6 7 8 SN54LVTH125 . . .
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SCBS703I − AUGUST 1997 − REVISED OCTOBER 2003 description/ordering information (continued) Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.
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SCBS703I − AUGUST 1997 − REVISED OCTOBER 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.
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SCBS703I − AUGUST 1997 − REVISED OCTOBER 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH VCC = 2.7 V, VCC = 2.7 V to 3.6 V, II = −18 mA IOH = −100 µA VCC = 2.7 V, IOH = −8 mA IOH = −24 mA VCC = 3 V VCC = 2.7 V VOL VCC = 3 V II Control inputs Data inputs Ioff SN54LVTH125 TYP† MAX TEST CONDITIONS MIN SN74LVTH125 TYP† MAX MIN −1.2 VCC−0.2 2.
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SCBS703I − AUGUST 1997 − REVISED OCTOBER 2003 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) SN54LVTH125 PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL A Y tPZH tPZL OE Y tPHZ tPLZ OE Y VCC = 3.3 V ± 0.3 V SN74LVTH125 VCC = 2.7 V VCC = 3.3 V ± 0.3 V VCC = 2.7 V MIN MAX MAX MIN TYP† MAX 1 4.2 4.7 1 2 3.5 4.5 1 4.1 5.
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SCBS703I − AUGUST 1997 − REVISED OCTOBER 2003 PARAMETER MEASUREMENT INFORMATION 6V 500 Ω From Output Under Test Open S1 GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 6V GND 2.7 V LOAD CIRCUIT Timing Input 1.5 V 0V tw tsu 2.7 V 1.5 V Input 1.5 V th 2.7 V 1.5 V Data Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V 1.5 V Input 1.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 9
PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PAGE 10
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74LVTH125DBR SSOP DB 14 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1 SN74LVTH125DGVR TVSOP DGV 14 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1 SN74LVTH125DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.
PAGE 11
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVTH125DBR SSOP DB 14 2000 367.0 367.0 38.0 SN74LVTH125DGVR TVSOP DGV 14 2000 367.0 367.0 35.0 SN74LVTH125DR SOIC D 14 2500 333.2 345.9 28.6 SN74LVTH125DR SOIC D 14 2500 367.0 367.0 38.0 SN74LVTH125NSR SO NS 14 2000 367.0 367.0 38.0 SN74LVTH125PWR TSSOP PW 14 2000 367.0 367.0 35.
PAGE 12
MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°– 8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.