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FEATURES

1OE

1Y1

1Y2

GND

1Y3

1Y4

2Y1

2Y2

GND

2Y3

2Y4

3Y1

3Y2

GND

3Y3

3Y4

4Y1

4Y2

GND

4Y3

4Y4

4OE

2OE

1A1

1A2

GND

1A3

1A4

2A1

2A2

GND

2A3

2A4

3A1

3A2

GND

3A3

3A4

4A1

4A2

GND

4A3

4A4

3OE

SN54LVTH162240. . . WD PACKAGE

SN74LVTH162240. . . DGG OR DL PACKAGE

(TOP VIEW)

DESCRIPTION/ORDERING INFORMATION

SN54LVTH162240 , , SN74LVTH162240

3.3-V ABT 16-BIT BUFFERS/DRIVERS

WITH 3-STATE OUTPUTS

SCBS685F – MARCH 1997 – REVISED NOVEMBER 2006

• Members of the Texas Instruments Widebus™

Family

• State-of-the-Art Advanced BiCMOS

Technology (ABT) Design for 3.3-V Operation

and Low Static-Power Dissipation

• Output Ports Have Equivalent 22- Ω Series

Resistors, So No External Resistors Are

Required

• Support Mixed-Mode Signal Operation

(5-V Input and Output Voltages With

3.3-V V

)

• Support Unregulated Battery Operation Down

to 2.7 V

• Typical V

OLP

(Output Ground Bounce) <0.8 V

at V

= 3.3 V, T

= 25 ° C

• I

off

and Power-Up 3-State Support Hot

Insertion

• Bus Hold on Data Inputs Eliminates the Need

for External Pullup/Pulldown Resistors

• Distributed V

and GND Pin Configuration

Minimizes High-Speed Switching Noise

• Flow-Through Architecture Optimizes PCB

Layout

• Latch-Up Performance Exceeds 250 mA Per

JESD 17

• ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

• Package Options Include Plastic Shrink

Small-Outline (DL) and Thin Shrink

Small-Outline (DGG) Packages and 380-mil

Fine-Pitch Ceramic Flat (WD) Package Using

25-mil Center-to-Center Spacings

The 'LVTH162240 devices are 16-bit buffers/drivers designed specifically for low-voltage (3.3-V) V

operation

and to improve both the performance and density of 3-state memory address drivers, clock drivers, and

bus-oriented receivers and transmitters. They have the capability to provide a TTL interface to a 5-V system

environment.

These devices can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer and provide inverting

outputs and symmetrical active-low output-enable ( OE) inputs.

The outputs, which are designed to source or sink up to 12 mA, include equivalent 22- Ω series resistors to

reduce overshoot and undershoot.

When V

is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down.

However, to ensure the high-impedance state above 1.5 V, OE should be tied to V

through a pullup resistor;

the minimum value of the resistor is determined by the current-sinking capability of the driver.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus is a trademark of Texas Instruments.

UNLESS OTHERWISE NOTED this document contains

PRODUCTION DATA information current as of publication date.

Products conform to specifications per the terms of Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (14 pages)

PAGE 1
SN54LVTH162240,, SN74LVTH162240 3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS www.ti.com FEATURES • • • • • • • • • • • • • Members of the Texas Instruments Widebus™ Family State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static-Power Dissipation Output Ports Have Equivalent 22-Ω Series Resistors, So No External Resistors Are Required Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.
PAGE 2
SN54LVTH162240,, SN74LVTH162240 3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS www.ti.com SCBS685F – MARCH 1997 – REVISED NOVEMBER 2006 DESCRIPTION/ORDERING INFORMATION (CONTINUED) Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. These devices are fully specified for hot-insertion applications using Ioff and power-up 3-state.
PAGE 3
SN54LVTH162240,, SN74LVTH162240 3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS www.ti.
PAGE 4
SN54LVTH162240,, SN74LVTH162240 3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS www.ti.
PAGE 5
SN54LVTH162240,, SN74LVTH162240 3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS www.ti.com SCBS685F – MARCH 1997 – REVISED NOVEMBER 2006 Recommended Operating Conditions (1) SN54LVTH162240 (2) SN74LVTH162240 MIN MAX MIN MAX 2.7 3.6 2.7 3.6 UNIT VCC Supply voltage VIH High-level input voltage VIL Low-level input voltage 0.8 0.8 VI Input voltage 5.5 5.
PAGE 6
SN54LVTH162240,, SN74LVTH162240 3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS www.ti.com SCBS685F – MARCH 1997 – REVISED NOVEMBER 2006 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (2) SN74LVTH162240 MAX MIN TYP (2) VCC = 2.7 V, II = –18 mA VOH VCC = 3 V, IOH = –12 mA VOL VCC = 3 V, IOL = 12 mA 0.8 0.8 VCC = 0 or 3.6 V, VI = 5.5 V 10 10 VCC = 3.
PAGE 7
SN54LVTH162240,, SN74LVTH162240 3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS www.ti.com SCBS685F – MARCH 1997 – REVISED NOVEMBER 2006 Switching Characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) SN54LVTH162240 (1) PARAMETER TO (OUTPUT) VCC = 3.3 V ± 0.3 V SN74LVTH162240 VCC = 3.3 V ± 0.3 V VCC = 2.7 V 1 4.2 5 1 2.5 4 4.6 1 4.2 5 1 2.9 4 4.6 1 5 5.5 1 2.8 4.8 5.7 1 4.9 5.1 1 2.8 4.7 4.9 1.9 4.
PAGE 8
SN54LVTH162240,, SN74LVTH162240 3.3-V ABT 16-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS www.ti.com SCBS685F – MARCH 1997 – REVISED NOVEMBER 2006 PARAMETER MEASUREMENT INFORMATION 500 Ω From Output Under Test 6V Open S1 GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 6V GND 2.7 V LOAD CIRCUIT Timing Input 1.5 V 0V tw tsu 2.7 V 1.5 V Input 1.5 V th 2.7 V Data Input 1.5 V 1.
PAGE 9
PACKAGE OPTION ADDENDUM www.ti.
PAGE 10
PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SN74LVTH162240DGGR TSSOP SN74LVTH162240DLR SSOP SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DGG 48 2000 330.0 24.4 8.6 15.8 1.8 12.0 24.0 Q1 DL 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.
PAGE 11
PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVTH162240DGGR TSSOP DGG 48 2000 346.0 346.0 41.0 SN74LVTH162240DLR SSOP DL 48 1000 346.0 346.0 49.
PAGE 12
MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
PAGE 13
MECHANICAL DATA MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0.025 (0,635) 0.0135 (0,343) 0.008 (0,203) 48 0.005 (0,13) M 25 0.010 (0,25) 0.005 (0,13) 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 0°–ā8° 24 0.040 (1,02) A 0.020 (0,51) Seating Plane 0.110 (2,79) MAX 0.004 (0,10) 0.008 (0,20) MIN PINS ** 28 48 56 A MAX 0.380 (9,65) 0.630 (16,00) 0.730 (18,54) A MIN 0.370 (9,40) 0.
PAGE 14
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.