Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICs74LVTH SSOP 56

 

     

  

SCBS700F − JULY 1997 − REVISED AUGUST 2009

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Members of the Texas Instruments

Widebus Family

D UBT  Transceiver Combines D-Type

Latches and D-Type Flip-Flops for

Operation in Transparent, Latched, or

Clocked Mode

D State-of-the-Art Advanced BiCMOS

Technology (ABT) Design for 3.3-V

Operation and Low Static-Power

Dissipation

D Support Mixed-Mode Signal Operation (5-V

Input and Output Voltages With 3.3-V V

)

D Support Unregulated Battery Operation

Down to 2.7 V

D Typical V

OLP

(Output Ground Bounce)

<0.8 V at V

= 3.3 V, T

= 25°C

D I

off

and Power-Up 3-State Support Hot

Insertion

D Bus Hold on Data Inputs Eliminates the

Need for External Pullup/Pulldown

Resistors

D Distributed V

and GND Pins Minimize

High-Speed Switching Noise

D Flow-Through Architecture Optimizes PCB

Layout

D Latch-Up Performance Exceeds 500 mA Per

JESD 17

D ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

description/ordering information

The ’LVTH16501 devices are 18-bit universal bus transceivers designed for low-voltage (3.3-V) V

operation,

but with the capability to provide a TTL interface to a 5-V system environment.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

SSOP − DL

Tube SN74LVTH16501DL

LVTH16501

−40°C to 85°C

SSOP − DL

Tape and reel SN74LVTH16501DLR

LVTH16501

−40 C to 85 C

TSSOP − DGG Tape and reel SN74LVTH16501DGGR LVTH16501

−55°C to 125°C CFP − WD Tube SNJ54LVTH16501WD SNJ54LVTH16501WD

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available

at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus and UBT are trademarks of Texas Instruments.

SN54LVTH16501 . . . WD PACKAGE

SN74LVTH16501 ... DGG OR DL PACKAGE

(TOP VIEW)

OEAB

LEAB

GND

A10

A11

A12

GND

A13

A14

A15

A16

A17

GND

A18

OEBA

LEBA

GND

CLKAB

GND

B10

B11

B12

GND

B13

B14

B15

B16

B17

GND

B18

CLKBA

GND

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Summary of content (15 pages)

PAGE 1
SCBS700F − JULY 1997 − REVISED AUGUST 2009 D Members of the Texas Instruments D D D D D D D D D D D SN54LVTH16501 . . . WD PACKAGE SN74LVTH16501 . . . DGG OR DL PACKAGE (TOP VIEW) Widebus  Family UBT  Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.
PAGE 2
SCBS700F − JULY 1997 − REVISED AUGUST 2009 description/ordering information (continued) Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the devices operate in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level.
PAGE 3
SCBS700F − JULY 1997 − REVISED AUGUST 2009 logic diagram (positive logic) OEAB CLKAB LEAB LEBA CLKBA OEBA A1 1 55 2 28 30 27 3 1D C1 CLK 54 B1 1D C1 CLK To 17 Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 4
SCBS700F − JULY 1997 − REVISED AUGUST 2009 recommended operating conditions (see Note 4) SN54LVTH16501 SN74LVTH16501 MIN MAX MIN MAX 2.7 3.6 2.7 3.6 UNIT VCC VIH Supply voltage VIL VI Low-level input voltage 0.8 0.8 Input voltage 5.5 5.
PAGE 5
SCBS700F − JULY 1997 − REVISED AUGUST 2009 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH VCC = 2.7 V, VCC = 2.7 V to 3.6 V, II = −18 mA IOH = −100 µA VCC = 2.7 V, IOH = −8 mA IOH = −24 mA VCC = 3 V VCC = 2.7 V VOL VCC = 3 V Control inputs VCC = 3.6 V, VCC = 0 or 3.
PAGE 6
SCBS700F − JULY 1997 − REVISED AUGUST 2009 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) SN54LVTH16501 VCC = 3.3 V ± 0.3 V MIN fclock tw tsu Clock frequency Pulse duration MIN 150 MAX MIN 150 MAX VCC = 2.7 V MIN 150 3.3 3.3 3.3 CLK high or low 3.3 3.3 3.3 3.3 A before CLKAB↑ 2.5 2.8 2.1 2.4 B before CLKBA↑ 2.5 2.8 2.1 2.
PAGE 7
SCBS700F − JULY 1997 − REVISED AUGUST 2009 PARAMETER MEASUREMENT INFORMATION 6V S1 500 Ω From Output Under Test GND CL = 50 pF (see Note A) TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 6V GND Open 500 Ω 2.7 V Timing Input LOAD CIRCUIT 1.5 V 0V tw tsu 2.7 V Input 1.5 V 1.5 V th 2.7 V Data Input 1.5 V 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V 1.
PAGE 8
PACKAGE OPTION ADDENDUM www.ti.
PAGE 9
PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
PAGE 10
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74LVTH16501DGGR TSSOP DGG 56 2000 330.0 24.4 8.6 15.6 1.8 12.0 24.0 Q1 SN74LVTH16501DLR SSOP DL 56 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.
PAGE 11
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVTH16501DGGR TSSOP DGG 56 2000 367.0 367.0 45.0 SN74LVTH16501DLR SSOP DL 56 1000 367.0 367.0 55.
PAGE 12
MECHANICAL DATA MCFP010B – JANUARY 1995 – REVISED NOVEMBER 1997 WD (R-GDFP-F**) CERAMIC DUAL FLATPACK 48 LEADS SHOWN 0.120 (3,05) 0.075 (1,91) 0.009 (0,23) 0.004 (0,10) 1.130 (28,70) 0.870 (22,10) 0.370 (9,40) 0.250 (6,35) 0.390 (9,91) 0.370 (9,40) 0.370 (9,40) 0.250 (6,35) 48 1 0.025 (0,635) A 0.014 (0,36) 0.008 (0,20) 25 24 NO. OF LEADS** 48 56 A MAX 0.640 (16,26) 0.740 (18,80) A MIN 0.610 (15,49) 0.710 (18,03) 4040176 / D 10/97 NOTES: A. B. C. D. E.
PAGE 13
PAGE 14
MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
PAGE 15
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.