Datasheet

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SN54LVTH16543, SN74LVTH16543

3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS

WITH 3-STATE OUTPUTS

SCBS699D – JULY 1997 – REVISED APRIL 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Members of the Texas Instruments

Widebus

 Family

State-of-the-Art Advanced BiCMOS

Technology (ABT) Design for 3.3-V

Operation and Low Static-Power

Dissipation

Support Mixed-Mode Signal Operation (5-V

Input and Output Voltages With 3.3-V V

)

Support Unregulated Battery Operation

Down to 2.7 V

off

and Power-Up 3-State Support Hot

Insertion

Bus Hold on Data Inputs Eliminates the

Need for External Pullup/Pulldown

Resistors

Typical V

OLP

(Output Ground Bounce)

< 0.8 V at V

= 3.3 V, T

= 25°C

Distributed V

and GND Pin Configuration

Minimizes High-Speed Switching Noise

Flow-Through Architecture Optimizes PCB

Layout

Latch-Up Performance Exceeds 500 mA Per

JESD 17

ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

Package Options Include Plastic Shrink

Small-Outline (DL) and Thin Shrink

Small-Outline (DGG) Packages and 380-mil

Fine-Pitch Ceramic Flat (WD) Package

Using 25-mil Center-to-Center Spacings

description

The ’LVTH16543 devices are 16-bit registered transceivers designed for low-voltage (3.3-V) V

operation, but

with the capability to provide a TTL interface to a 5-V system environment. These devices can be used as two

8-bit transceivers or one 16-bit transceiver. Separate latch-enable (LEAB

or LEBA) and output-enable (OEAB

or OEBA) inputs are provided for each register to permit independent control in either direction of data flow.

The A-to-B enable (CEAB

) input must be low to enter data from A or to output data from B. If CEAB is low and

LEAB

is low, the A-to-B latches are transparent; a subsequent low-to-high transition of LEAB puts the A latches

in the storage mode. With CEAB

and OEAB both low, the 3-state B outputs are active and reflect the data present

at the output of the A latches. Data flow from B to A is similar but requires using the CEBA

, LEBA, and OEBA

inputs.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus is a trademark of Texas Instruments Incorporated.

SN54LVTH16543 . . . WD PACKAGE

SN74LVTH16543 ... DGG OR DL PACKAGE

(TOP VIEW)

1OEAB

1LEAB

1CEAB

GND

1A1

1A2

1A3

1A4

1A5

GND

1A6

1A7

1A8

2A1

2A2

2A3

GND

2A4

2A5

2A6

2A7

2A8

GND

2CEAB

2LEAB

2OEAB

1OEBA

1LEBA

1CEBA

GND

1B1

1B2

1B3

1B4

1B5

GND

1B6

1B7

1B8

2B1

2B2

2B3

GND

2B4

2B5

2B6

2B7

2B8

GND

2CEBA

2LEBA

2OEBA

Summary of content (14 pages)

PAGE 1
SN54LVTH16543, SN74LVTH16543 3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS699D – JULY 1997 – REVISED APRIL 1999 D D D D D D D D D D D D Members of the Texas Instruments Widebus  Family State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static-Power Dissipation Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC) Support Unregulated Battery Operation Down to 2.
PAGE 2
SN54LVTH16543, SN74LVTH16543 3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS699D – JULY 1997 – REVISED APRIL 1999 description (continued) When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
PAGE 3
SN54LVTH16543, SN74LVTH16543 3.
PAGE 4
SN54LVTH16543, SN74LVTH16543 3.
PAGE 5
SN54LVTH16543, SN74LVTH16543 3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS699D – JULY 1997 – REVISED APRIL 1999 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 6
SN54LVTH16543, SN74LVTH16543 3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS699D – JULY 1997 – REVISED APRIL 1999 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH VCC = 2.7 V, VCC = 2.7 V to 3.6 V, II = –18 mA IOH = –100 µA VCC = 2.7 V, IOH = –8 mA IOH = –24 mA VCC = 3 V 7V VCC = 2 2.7 VOL VCC = 3 V Control inputs Ioff II(hold) ( ) A or B ports MIN –1.2 VCC–0.2 2.4 –1.2 VCC–0.2 2.4 0.
PAGE 7
SN54LVTH16543, SN74LVTH16543 3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS699D – JULY 1997 – REVISED APRIL 1999 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) SN54LVTH16543 VCC = 3.3 V ± 0.3 V MIN tw tsu th Pulse duration, LEAB or LEBA low VCC = 2.7 V MIN MAX MIN MAX VCC = 2.7 V MIN 3.3 3.3 3.3 3.3 A or B before LEAB↑ or LEBA↑ Data high 0.5 0.5 0.5 0.5 Data low 0.8 1.3 0.8 1.
PAGE 8
SN54LVTH16543, SN74LVTH16543 3.3-V ABT 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS SCBS699D – JULY 1997 – REVISED APRIL 1999 PARAMETER MEASUREMENT INFORMATION 6V 500 Ω From Output Under Test S1 GND CL = 50 pF (see Note A) TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 6V GND Open 500 Ω 2.7 V 1.5 V Timing Input LOAD CIRCUIT 0V tw tsu 2.7 V Input 1.5 V 1.5 V th 2.7 V 1.5 V Data Input 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V 1.
PAGE 9
PACKAGE OPTION ADDENDUM www.ti.
PAGE 10
PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74LVTH16543DGGR TSSOP DGG 56 2000 330.0 24.4 8.6 15.6 1.8 12.0 24.0 Q1 SN74LVTH16543DLR SSOP DL 56 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.
PAGE 11
PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVTH16543DGGR TSSOP DGG 56 2000 346.0 346.0 41.0 SN74LVTH16543DLR SSOP DL 56 1000 346.0 346.0 49.
PAGE 12
MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
PAGE 13
MECHANICAL DATA MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0.025 (0,635) 0.0135 (0,343) 0.008 (0,203) 48 0.005 (0,13) M 25 0.010 (0,25) 0.005 (0,13) 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 0°–ā8° 24 0.040 (1,02) A 0.020 (0,51) Seating Plane 0.110 (2,79) MAX 0.004 (0,10) 0.008 (0,20) MIN PINS ** 28 48 56 A MAX 0.380 (9,65) 0.630 (16,00) 0.730 (18,54) A MIN 0.370 (9,40) 0.
PAGE 14
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