Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Receiver, transceiver SSOP 56

 

      

  

SCBS698G − JULY 1997 − REVISED MAY 2004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Members of the Texas Instruments

Widebus Family

D State-of-the-Art Advanced BiCMOS

Technology (ABT) Design for 3.3-V

Operation and Low Static-Power

Dissipation

D Support Mixed-Mode Signal Operation

(5-V Input and Output Voltages With

3.3-V V

)

D Support Unregulated Battery Operation

Down to 2.7 V

D Typical V

OLP

(Output Ground Bounce)

<0.8 V at V

= 3.3 V, T

= 25°C

D I

off

and Power-Up 3-State Support Hot

Insertion

D Bus Hold on Data Inputs Eliminates the

Need for External Pullup/Pulldown

Resistors

D Distributed V

and GND Pin Configuration

Minimizes High-Speed Switching Noise

D Flowthrough Architecture Optimizes PCB

Layout

D Latch-Up Performance Exceeds 500 mA Per

JESD 17

D ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

description/ordering information

The ’LVTH16646 devices are 16-bit bus

transceivers and registers designed for

low-voltage (3.3-V) V

operation, but with the

capability to provide a TTL interface to a 5-V

system environment.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

SSOP − DL

Tube SN74LVTH16646DL

LVTH16646

−40°C to 85°C

SSOP − DL

Tape and reel SN74LVTH16646DLR

LVTH16646

−40 C to 85 C

TSSOP − DGG Tape and reel SN74LVTH16646DGGR LVTH16646

−55°C to 125°C CFP − WD Tube SNJ54LVTH16646WD SNJ54LVTH16646WD

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available

at www.ti.com/sc/package.

    !"#$%&' #"'(' 

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*"!$#"' +*"#&'1 !"& '" '&#&(*-0 '#-$!& &'1 ") (--

+(*(%&&*

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus is a trademark of Texas Instruments.

SN54LVTH16646 . . . WD PACKAGE

SN74LVTH16646 ... DGG OR DL PACKAGE

(TOP VIEW)

1DIR

1CLKAB

1SAB

GND

1A1

1A2

1A3

1A4

1A5

GND

1A6

1A7

1A8

2A1

2A2

2A3

GND

2A4

2A5

2A6

2A7

2A8

GND

2SAB

2CLKAB

2DIR

1OE

1CLKBA

1SBA

GND

1B1

1B2

1B3

1B4

1B5

GND

1B6

1B7

1B8

2B1

2B2

2B3

GND

2B4

2B5

2B6

2B7

2B8

GND

2SBA

2CLKBA

2OE

Summary of content (14 pages)

PAGE 1
SCBS698G − JULY 1997 − REVISED MAY 2004 D Members of the Texas Instruments D D D D D D D D D D SN54LVTH16646 . . . WD PACKAGE SN74LVTH16646 . . . DGG OR DL PACKAGE (TOP VIEW) Widebus  Family State-of-the-Art Advanced BiCMOS Technology (ABT) Design for 3.3-V Operation and Low Static-Power Dissipation Support Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.
PAGE 2
SCBS698G − JULY 1997 − REVISED MAY 2004 description/ordering information (continued) These devices can be used as two 8-bit transceivers or one 16-bit transceiver. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed with the ’LVTH16646 devices.
PAGE 3
OE L DIR L CLKAB CLKBA X X SAB X BUS B BUS A BUS A BUS B SCBS698G − JULY 1997 − REVISED MAY 2004 SBA L OE L DIR H DIR X X X CLKAB CLKBA ↑ X ↑ X ↑ ↑ SAB L SBA X BUS B BUS A BUS A OE X X H CLKBA X REAL-TIME TRANSFER BUS A TO BUS B BUS B REAL-TIME TRANSFER BUS B TO BUS A CLKAB X SAB SBA X X X X X X STORAGE FROM A, B, OR A AND B OE L L DIR L H CLKAB X H or L CLKBA H or L X SAB X H SBA H X
PAGE 4
SCBS698G − JULY 1997 − REVISED MAY 2004 logic diagram (positive logic) 1OE 1DIR 1CLKBA 1SBA 1CLKAB 1SAB 56 1 55 54 2 3 One of Eight Channels 1D C1 1A1 5 52 1B1 1D C1 2OE 2DIR 2CLKBA 2SBA 2CLKAB 2SAB To Seven Other Channels 29 28 30 31 27 26 One of Eight Channels 1D C1 2A1 15 42 1D C1 To Seven Other Channels 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 2B1
PAGE 5
SCBS698G − JULY 1997 − REVISED MAY 2004 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 6
SCBS698G − JULY 1997 − REVISED MAY 2004 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH VCC = 2.7 V, VCC = 2.7 V to 3.6 V, II = −18 mA IOH = −100 µA VCC = 2.7 V, IOH = −8 mA IOH = −24 mA VCC = 3 V VOL VCC = 3 V Ioff II(hold) A or B ports SN74LVTH16646 TYP† MAX MIN −1.2 VCC−0.2 2.4 −1.2 2 0.2 0.2 IOL = 24 mA IOL = 16 mA 0.5 0.
PAGE 7
SCBS698G − JULY 1997 − REVISED MAY 2004 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 2) SN54LVTH16646 VCC = 3.3 V ± 0.3 V MIN fclock tw Clock frequency MAX SN74LVTH16646 VCC = 2.
PAGE 8
SCBS698G − JULY 1997 − REVISED MAY 2004 PARAMETER MEASUREMENT INFORMATION 6V S1 500 Ω From Output Under Test GND CL = 50 pF (see Note A) TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 6V GND Open 500 Ω 2.7 V Timing Input LOAD CIRCUIT 1.5 V 0V tw tsu 2.7 V Input 1.5 V 1.5 V th 2.7 V Data Input 1.5 V 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V 1.
PAGE 9
PACKAGE OPTION ADDENDUM www.ti.
PAGE 10
PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74LVTH16646DGGR TSSOP DGG 56 2000 330.0 24.4 8.6 15.6 1.8 12.0 24.0 Q1 SN74LVTH16646DLR SSOP DL 56 1000 330.0 32.4 11.35 18.67 3.1 16.0 32.
PAGE 11
PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVTH16646DGGR TSSOP DGG 56 2000 346.0 346.0 41.0 SN74LVTH16646DLR SSOP DL 56 1000 346.0 346.0 49.
PAGE 12
MECHANICAL DATA MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0.025 (0,635) 0.0135 (0,343) 0.008 (0,203) 48 0.005 (0,13) M 25 0.010 (0,25) 0.005 (0,13) 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 0°–ā8° 24 0.040 (1,02) A 0.020 (0,51) Seating Plane 0.110 (2,79) MAX 0.004 (0,10) 0.008 (0,20) MIN PINS ** 28 48 56 A MAX 0.380 (9,65) 0.630 (16,00) 0.730 (18,54) A MIN 0.370 (9,40) 0.
PAGE 13
MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
PAGE 14
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.