SN54LVTH18512, SN54LVTH182512, SN74LVTH18512, SN74LVTH182512 3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS671B – AUGUST 1996 – REVISED OCTOBER 1997 D D D D D D D D D D Members of the Texas Instruments SCOPE Family of Testability Products Members of the Texas Instruments Widebus Family State-of-the-Art 3.3-V ABT Design Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC) Support Unregulated Battery Operation Down to 2.
SN54LVTH18512, SN54LVTH182512, SN74LVTH18512, SN74LVTH182512 3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS671B – AUGUST 1996 – REVISED OCTOBER 1997 description (continued) In the normal mode, these devices are 18-bit universal bus transceivers that combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, or clocked modes. They can be used either as two 9-bit transceivers or one 18-bit transceiver.
SN54LVTH18512, SN54LVTH182512, SN74LVTH18512, SN74LVTH182512 3.
SN54LVTH18512, SN54LVTH182512, SN74LVTH18512, SN74LVTH182512 3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS671B – AUGUST 1996 – REVISED OCTOBER 1997 Terminal Functions TERMINAL NAME Normal-function A-bus I/O ports. See function table for normal-mode logic. 1B1–1B9, 2B1–2B9 Normal-function B-bus I/O ports. See function table for normal-mode logic. 1CLKAB, 1CLKBA, 2CLKAB, 2CLKBA GND 4 DESCRIPTION 1A1–1A9, 2A1–2A9 Normal-function clock inputs.
SN54LVTH18512, SN54LVTH182512, SN74LVTH18512, SN74LVTH182512 3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS671B – AUGUST 1996 – REVISED OCTOBER 1997 test architecture Serial-test information is conveyed by means of a 4-wire test bus or TAP, that conforms to IEEE Std 1149.1-1990. Test instructions, test data, and test control signals all are passed along this serial-test bus. The TAP controller monitors two signals from the test bus, TCK and TMS.
SN54LVTH18512, SN54LVTH182512, SN74LVTH18512, SN74LVTH182512 3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS671B – AUGUST 1996 – REVISED OCTOBER 1997 state diagram description The TAP controller is a synchronous finite-state machine that provides test control signals throughout the device. The state diagram shown in Figure 1 is in accordance with IEEE Std 1149.1-1990. The TAP controller proceeds through its states based on the level of TMS at the rising edge of TCK.
SN54LVTH18512, SN54LVTH182512, SN74LVTH18512, SN74LVTH182512 3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS671B – AUGUST 1996 – REVISED OCTOBER 1997 Shift-DR Upon entry to the Shift-DR state, the data register is placed in the scan path between TDI and TDO, and on the first falling edge of TCK, TDO goes from the high-impedance state to an active state. TDO enables to the logic level present in the least-significant bit of the selected data register.
SN54LVTH18512, SN54LVTH182512, SN74LVTH18512, SN74LVTH182512 3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS671B – AUGUST 1996 – REVISED OCTOBER 1997 register overview With the exception of the bypass and device-identification registers, any test register can be thought of as a serial shift register with a shadow latch on each bit. The bypass and device-identification registers differ in that they contain only a shift register.
SN54LVTH18512, SN54LVTH182512, SN74LVTH18512, SN74LVTH182512 3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS671B – AUGUST 1996 – REVISED OCTOBER 1997 data register description boundary-scan register The boundary-scan register (BSR) is 48 bits long. It contains one boundary-scan cell (BSC) for each normal-function input pin and one BSC for each normal-function I/O pin (one single cell for both input data and output data).
SN54LVTH18512, SN54LVTH182512, SN74LVTH18512, SN74LVTH182512 3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS671B – AUGUST 1996 – REVISED OCTOBER 1997 boundary-control register The boundary-control register (BCR) is three bits long. The BCR is used in the context of the boundary-run test (RUNT) instruction to implement additional test operations not included in the basic SCOPE instruction set. Such operations include PRPG, PSA, and binary count up (COUNT).
SN54LVTH18512, SN54LVTH182512, SN74LVTH18512, SN74LVTH182512 3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS671B – AUGUST 1996 – REVISED OCTOBER 1997 device-identification register The device-identification register (IDR) is 32 bits long. It can be selected and read to identify the manufacturer, part number, and version of this device.
SN54LVTH18512, SN54LVTH182512, SN74LVTH18512, SN74LVTH182512 3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS671B – AUGUST 1996 – REVISED OCTOBER 1997 instruction-register opcode description The instruction-register opcodes are shown in Table 3. The following descriptions detail the operation of each instruction. Table 3.
SN54LVTH18512, SN54LVTH182512, SN74LVTH18512, SN74LVTH182512 3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS671B – AUGUST 1996 – REVISED OCTOBER 1997 bypass scan This instruction conforms to the IEEE Std 1149.1-1990 BYPASS instruction. The bypass register is selected in the scan path. A logic 0 value is captured in the bypass register during Capture-DR. The device operates in the normal mode. control boundary to high impedance This instruction conforms to the IEEE Std 1149.
SN54LVTH18512, SN54LVTH182512, SN74LVTH18512, SN74LVTH182512 3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS671B – AUGUST 1996 – REVISED OCTOBER 1997 boundary-control-register opcode description The BCR opcodes are decoded from BCR bits 2–0 as shown in Table 4. The selected test operation is performed while the RUNT instruction is executed in the Run-Test /Idle state.
SN54LVTH18512, SN54LVTH182512, SN74LVTH18512, SN74LVTH182512 3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS671B – AUGUST 1996 – REVISED OCTOBER 1997 pseudo-random pattern generation (PRPG) A pseudo-random pattern is generated in the shift-register elements of the selected BSCs on each rising edge of TCK, updated in the shadow latches, and applied to the associated device output-mode I/O pins on each falling edge of TCK.
SN54LVTH18512, SN54LVTH182512, SN74LVTH18512, SN74LVTH182512 3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS671B – AUGUST 1996 – REVISED OCTOBER 1997 2B9-I/O 2B8-I/O 2B7-I/O 2B6-I/O 2B5-I/O 2B4-I/O 2B3-I/O 2B2-I/O 2B1-I/O 1B9-I/O 1B8-I/O 1B7-I/O 1B6-I/O 1B5-I/O 1B4-I/O 1B3-I/O 1B2-I/O 1B1-I/O 2A9-I/O 2A8-I/O 2A7-I/O 2A6-I/O 2A5-I/O 2A4-I/O 2A3-I/O 2A2-I/O 2A1-I/O 1A9-I/O 1A8-I/O 1A7-I/O 1A6-I/O 1A5-I/O 1A4-I/O 1A3-I/O 1A2-I/O 1A1-I/O = Figure 6.
SN54LVTH18512, SN54LVTH182512, SN74LVTH18512, SN74LVTH182512 3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS671B – AUGUST 1996 – REVISED OCTOBER 1997 parallel-signature analysis (PSA) Data appearing at the selected device input-mode I/O pins is compressed into a 36-bit parallel signature in the shift-register elements of the selected BSCs on each rising edge of TCK.
SN54LVTH18512, SN54LVTH182512, SN74LVTH18512, SN74LVTH182512 3.
SN54LVTH18512, SN54LVTH182512, SN74LVTH18512, SN74LVTH182512 3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS671B – AUGUST 1996 – REVISED OCTOBER 1997 simultaneous PSA and PRPG (PSA/PRPG) Data appearing at the selected device input-mode I/O pins is compressed into an 18-bit parallel signature in the shift-register elements of the selected input-mode BSCs on each rising edge of TCK.
SN54LVTH18512, SN54LVTH182512, SN74LVTH18512, SN74LVTH182512 3.
SN54LVTH18512, SN54LVTH182512, SN74LVTH18512, SN74LVTH182512 3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS671B – AUGUST 1996 – REVISED OCTOBER 1997 simultaneous PSA and binary count up (PSA/COUNT) Data appearing at the selected device input-mode I/O pins is compressed into an 18-bit parallel signature in the shift-register elements of the selected input-mode BSCs on each rising edge of TCK.
SN54LVTH18512, SN54LVTH182512, SN74LVTH18512, SN74LVTH182512 3.
SN54LVTH18512, SN54LVTH182512, SN74LVTH18512, SN74LVTH182512 3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS671B – AUGUST 1996 – REVISED OCTOBER 1997 timing description All test operations of the ’LVTH18512 and ’LVTH182512 are synchronous to the TCK signal. Data on the TDI, TMS, and normal-function inputs is captured on the rising edge of TCK. Data appears on the TDO and normal-function output pins on the falling edge of TCK.
SN54LVTH18512, SN54LVTH182512, SN74LVTH18512, SN74LVTH182512 3.
SN54LVTH18512, SN54LVTH182512, SN74LVTH18512, SN74LVTH182512 3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS671B – AUGUST 1996 – REVISED OCTOBER 1997 recommended operating conditions (see Note 4) SN54LVTH18512 SN74LVTH18512 MIN MAX MIN MAX 2.7 3.6 2.7 3.6 UNIT VCC VIH Supply voltage VIL VI Low-level input voltage 0.8 0.8 Input voltage 5.5 5.
SN54LVTH18512, SN54LVTH182512, SN74LVTH18512, SN74LVTH182512 3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS671B – AUGUST 1996 – REVISED OCTOBER 1997 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK II = –18 mA IOH = –100 µA VCC = 2.7 V, IOH = –3 mA IOH = –8 mA VCC = 3 V IOH = –24 mA IOH = –32 mA VCC = 2 2.7 7V VOL VCC = 3 V IOZH IOZL TDO IOZPU IOZPD TDO ICC TDO TDO VCC = 3.6 V, VCC = 3.
SN54LVTH18512, SN54LVTH182512, SN74LVTH18512, SN74LVTH182512 3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS671B – AUGUST 1996 – REVISED OCTOBER 1997 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (normal mode) (see Figure 14) SN54LVTH18512 VCC = 3.3 V ± 0.
SN54LVTH18512, SN54LVTH182512, SN74LVTH18512, SN74LVTH182512 3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS671B – AUGUST 1996 – REVISED OCTOBER 1997 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (normal mode) (see Figure 14) SN54LVTH18512 PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 3.3 V ± 0.
SN54LVTH18512, SN54LVTH182512, SN74LVTH18512, SN74LVTH182512 3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS671B – AUGUST 1996 – REVISED OCTOBER 1997 recommended operating conditions (see Note 4) SN54LVTH182512 SN74LVTH182512 MIN MAX MIN MAX 2.7 3.6 2.7 3.6 UNIT VCC VIH Supply voltage VIL VI Low-level input voltage 0.8 0.8 V Input voltage 5.5 5.
SN54LVTH18512, SN54LVTH182512, SN74LVTH18512, SN74LVTH182512 3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS671B – AUGUST 1996 – REVISED OCTOBER 1997 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK A, B, TDO VOH A port,, TDO B port A, B, TDO VOL A port, t TDO B port CLK, LE, TCK II OE, OE TDI TMS TDI, A or B orts‡ ports Ioff II(hold)§ IOZH IOZL TDO IOZPU IOZPD TDO ICC VCC = 2.7 V, VCC = 2.7 V to 3.
SN54LVTH18512, SN54LVTH182512, SN74LVTH18512, SN74LVTH182512 3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS671B – AUGUST 1996 – REVISED OCTOBER 1997 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (normal mode) (see Figure 14) SN54LVTH182512 VCC = 3.3 V ± 0.
SN54LVTH18512, SN54LVTH182512, SN74LVTH18512, SN74LVTH182512 3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS671B – AUGUST 1996 – REVISED OCTOBER 1997 switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (normal mode) (see Figure 14) SN54LVTH182512 PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 3.3 V ± 0.
SN54LVTH18512, SN54LVTH182512, SN74LVTH18512, SN74LVTH182512 3.3-V ABT SCAN TEST DEVICES WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS671B – AUGUST 1996 – REVISED OCTOBER 1997 PARAMETER MEASUREMENT INFORMATION 6V S1 500 Ω From Output Under Test Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 6V GND LOAD CIRCUIT 2.7 V 1.5 V Timing Input 0V tw tsu 2.7 V Input 1.5 V 2.7 V 1.5 V Data Input 1.5 V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V 1.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74LVTH182512DGGR TSSOP DGG 64 2000 330.0 24.4 8.4 17.3 1.7 12.0 24.0 Q1 SN74LVTH18512DGGR DGG 64 2000 330.0 24.4 8.4 17.3 1.7 12.0 24.
PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVTH182512DGGR TSSOP DGG 64 2000 346.0 346.0 41.0 SN74LVTH18512DGGR TSSOP DGG 64 2000 346.0 346.0 41.
MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
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