Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Flip-Flop Standard Three-state, Non-inverting TSSOP 20

 

     

  

SCBS683H − MARCH 1997 − REVISED OCTOBER 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Support Mixed-Mode Signal Operation

(5-V Input and Output Voltages With

3.3-V V

)

D Typical V

OLP

(Output Ground Bounce)

<0.8 V at V

= 3.3 V, T

= 25°C

D Support Unregulated Battery Operation

Down to 2.7 V

D I

off

and Power-Up 3-State Support Hot

Insertion

D Bus Hold on Data Inputs Eliminates the

Need for External Pullup/Pulldown

Resistors

D Latch-Up Performance Exceeds 500 mA Per

JESD 17

D ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

description/ordering information

These octal flip-flops are designed specifically for

low-voltage (3.3-V) V

operation, but with the

capability to provide a TTL interface to a

5-V system environment.

The eight flip-flops of the ’LVTH374 devices are

edge-triggered D-type flip-flops. On the positive

transition of the clock (CLK) input, the Q outputs

are set to the logic levels set up at the data (D)

inputs.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

SOIC − DW

Tube SN74LVTH374DW

LVTH374

SOIC − DW

Tape and reel SN74LVTH374DWR

LVTH374

−40°C to 85°C

SOP − NS Tape and reel SN74LVTH374NSR LVTH374

−40°C to 85°C

SSOP − DB Tape and reel SN74LVTH374DBR LXH374

TSSOP − PW

Tube SN74LVTH374PW

LXH374

TSSOP − PW

Tape and reel SN74LVTH374PWR

LXH374

CDIP − J Tube SNJ54LVTH374J SNJ54LVTH374J

−55°C to 125°C

CFP − W Tube SNJ54LVTH374W SNJ54LVTH374W

−55 C to 125 C

LCCC - FK Tube SNJ54LVTH374FK SNJ54LVTH374FK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SN54LVTH374 ...J OR W PACKAGE

SN74LVTH374 . . . DB, DW, NS, OR PW PACKAGE

(TOP VIEW)

SN54LVTH374 . . . FK PACKAGE

(TOP VIEW)

GND

CLK

3 2 1 20 19

9 10 11 12 13

GND

CLK

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#,%%(/ !,% $ ,#,%%)('0 (#'"!, $,%$(/ 1 )'' ))&,$,%

  (1&)$( (% #",$ )% 1 "2'(#)$( !)$,

!"#$% #1& $ %,#(1(#)$(% , $-, $,&% 1 ,3)% %$"&,$%

%$)!)! .))$0 !"#$( #,%%(/ !,% $ ,#,%%)('0 (#'"!,

$,%$(/ 1 )'' ))&,$,%

Summary of content (20 pages)

PAGE 1
SCBS683H − MARCH 1997 − REVISED OCTOBER 2003 D Support Mixed-Mode Signal Operation D D D D OE 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q CLK SN54LVTH374 . . . FK PACKAGE (TOP VIEW) description/ordering information 2D 2Q 3Q 3D 4D These octal flip-flops are designed specifically for low-voltage (3.
PAGE 2
SCBS683H − MARCH 1997 − REVISED OCTOBER 2003 description/ordering information (continued) A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly.
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SCBS683H − MARCH 1997 − REVISED OCTOBER 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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SCBS683H − MARCH 1997 − REVISED OCTOBER 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH TEST CONDITIONS VCC = 2.7 V, VCC = 2.7 V to 3.6 V, II = −18 mA IOH = −100 µA VCC = 2.7 V, IOH = −8 mA IOH = −24 mA VCC = 3 V Ioff II(hold) 2 0.5 0.4 0.4 IOL = 32 mA IOL = 48 mA 0.5 0.5 0.55 VCC = 0 or 3.6 V, IOL = 64 mA VI = 5.
PAGE 5
SCBS683H − MARCH 1997 − REVISED OCTOBER 2003 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) SN54LVTH374 VCC = 3.3 V ± 0.3 V MIN MAX SN74LVTH374 VCC = 3.3 V ± 0.3 V VCC = 2.7 V MIN MAX 150 MIN 150 MAX VCC = 2.7 V MIN 150 UNIT MAX fclock tw Clock frequency Pulse duration, CLK high or low 3.3 3.3 3.3 3.
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SCBS683H − MARCH 1997 − REVISED OCTOBER 2003 PARAMETER MEASUREMENT INFORMATION 500 Ω From Output Under Test 6V Open S1 GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 6V GND 2.7 V LOAD CIRCUIT Timing Input 1.5 V 0V tw tsu 2.7 V Input 1.5 V 1.5 V th 2.7 V Data Input 1.5 V 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V 1.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 9
PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device.
PAGE 10
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74LVTH374DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 SN74LVTH374DWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 SN74LVTH374NSR SO NS 20 2000 330.0 24.4 8.2 13.0 2.5 12.0 24.
PAGE 11
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVTH374DBR SN74LVTH374DWR SSOP DB 20 2000 367.0 367.0 38.0 SOIC DW 20 2000 367.0 367.0 45.0 SN74LVTH374NSR SO NS 20 2000 367.0 367.0 45.0 SN74LVTH374PWR TSSOP PW 20 2000 367.0 367.0 38.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.