Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Buffer, driver TSSOP 20

 

   

  

SCBS682G − MARCH 1997 − REVISED OCTOBER 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Support Mixed-Mode Signal Operation (5-V

Input and Output Voltages With 3.3-V V

)

D Typical V

OLP

(Output Ground Bounce)

<0.8 V at V

= 3.3 V, T

= 25°C

D Support Unregulated Battery Operation

Down to 2.7 V

D I

off

and Power-Up 3-State Support Hot

Insertion

D Bus Hold on Data Inputs Eliminates the

Need for External Pullup/Pulldown

Resistors

D Latch-Up Performance Exceeds 500 mA Per

JESD 17

D ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

description/ordering information

These octal buffers/drivers are designed

specifically for low-voltage (3.3-V) V

operation,

but with the capability to provide a TTL interface

to a 5-V system environment.

The ’LVTH541 devices are ideal for driving bus

lines or buffer-memory address registers. These

devices feature inputs and outputs on opposite

sides of the package that facilitate printed circuit

board layout.

The 3-state control gate is a 2-input AND gate with active-low inputs so that, if either output-enable (OE1

or OE2)

input is high, all outputs are in the high-impedance state.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

SOIC − DW

Tube SN74LVTH541DW

LVTH541

SOIC − DW

Tape and reel SN74LVTH541DWR

LVTH541

−40°C to 85°C

SOP − NS Tape and reel SN74LVTH541NSR LVTH541

−40°C to 85°C

SSOP − DB Tape and reel SN74LVTH541DBR LXH541

TSSOP − PW

Tube SN74LVTH541PW

LXH541

TSSOP − PW

Tape and reel SN74LVTH541PWR

LXH541

CDIP − J Tube SNJ54LVTH541J SNJ54LVTH541J

−55°C to 125°C

CFP − W Tube SNJ54LVTH541W SNJ54LVTH541W

−55 C to 125 C

LCCC - FK Tube SNJ54LVTH541FK SNJ54LVTH541FK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

    !"#$%&' #"'(' 

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

OE1

GND

OE2

SN54LVTH541 ...J OR W PACKAGE

SN74LVTH541 . . . DB, DW, NS, OR PW PACKAGE

(TOP VIEW)

3212019

910111213

SN54LVTH541 . . . FK PACKAGE

(TOP VIEW)

OE1

Y6 OE2

GND

Summary of content (16 pages)

PAGE 1
SCBS682G − MARCH 1997 − REVISED OCTOBER 2003 D Support Mixed-Mode Signal Operation (5-V D D D D OE1 A1 A2 A3 A4 A5 A6 A7 A8 GND 1 20 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC OE2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 SN54LVTH541 . . . FK PACKAGE (TOP VIEW) description/ordering information These octal buffers/drivers are designed specifically for low-voltage (3.
PAGE 2
SCBS682G − MARCH 1997 − REVISED OCTOBER 2003 description/ordering information (continued) Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended. When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.
PAGE 3
SCBS682G − MARCH 1997 − REVISED OCTOBER 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.
PAGE 4
SCBS682G − MARCH 1997 − REVISED OCTOBER 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOH VCC = 2.7 V, VCC = 2.7 V to 3.6 V, II = −18 mA IOH = −100 µA VCC = 2.7 V, IOH = −8 mA IOH = −24 mA VCC = 3 V VCC = 2.7 V VOL VCC = 3 V Control inputs II Data inputs Ioff II(hold) IOZH IOZL VCC = 0 or 3.6 V, VCC = 3.6 V, VCC = 3.
PAGE 5
SCBS682G − MARCH 1997 − REVISED OCTOBER 2003 switching characteristics over recommended ranges of supply voltage and operating free-air temperature, CL = 50 pF (unless otherwise noted) (see Figure 1) SN54LVTH541 PARAMETER FROM (INPUT) TO (OUTPUT) tPLH tPHL A Y tPZH tPZL OE1 or OE2 Y tPHZ tPLZ OE1 or OE2 Y VCC = 3.3 V ± 0.3 V SN74LVTH541 VCC = 2.7 V VCC = 3.3 V ± 0.3 V VCC = 2.7 V MIN MAX MAX MIN TYP† MAX 1 3.
PAGE 6
SCBS682G − MARCH 1997 − REVISED OCTOBER 2003 PARAMETER MEASUREMENT INFORMATION 500 Ω From Output Under Test 6V Open S1 GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPHL/tPLH tPLZ/tPZL tPHZ/tPZH Open 6V GND 2.7 V LOAD CIRCUIT Timing Input 1.5 V 0V tw tsu 2.7 V Input 1.5 V 1.5 V th 2.7 V Data Input 1.5 V 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V 1.5 V Input 1.
PAGE 7
PACKAGE OPTION ADDENDUM www.ti.
PAGE 8
PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe.
PAGE 9
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74LVTH541DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 SN74LVTH541DWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 SN74LVTH541NSR SO NS 20 2000 330.0 24.4 8.2 13.0 2.5 12.0 24.
PAGE 10
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVTH541DBR SN74LVTH541DWR SSOP DB 20 2000 367.0 367.0 38.0 SOIC DW 20 2000 367.0 367.0 45.0 SN74LVTH541NSR SO NS 20 2000 367.0 367.0 45.0 SN74LVTH541PWR TSSOP PW 20 2000 367.0 367.0 38.
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PAGE 15
MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
PAGE 16
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.