Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Latch Transparent D latch Three-state TSSOP 20

SN54LVTH573, SN74LVTH573

3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES

WITH 3-STATE OUTPUTS

SCBS687H − MAY 1997 − REVISED SEPTEMBER 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Support Mixed-Mode Signal Operation

(5-V Input and Output Voltages With

3.3-V V

)

D Support Unregulated Battery Operation

Down to 2.7 V

D Typical V

OLP

(Output Ground Bounce)

<0.8 V at V

= 3.3 V, T

= 25°C

D I

off

and Power-Up 3-State Support Hot

Insertion

D Bus Hold on Data Inputs Eliminates the

Need for External Pullup/Pulldown

Resistors

D Latch-Up Performance Exceeds 500 mA Per

JESD 17

D ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

SN54LVTH573 ...J OR W PACKAGE

SN74LVTH573 . . . DB, DW, NS,

OR PW PACKAGE

(TOP VIEW)

SN54LVTH573 . . . FK PACKAGE

(TOP VIEW)

GND

3212019

910111213

7Q 1Q

GND

SN74LVTH573 . . . RGY PACKAGE

(TOP VIEW)

120

10 11

GND

description/ordering information

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE MARKING

QFN − RGY Tape and reel SN74LVTH573RGYR LXH573

SOIC DW

Tube SN74LVTH573DW LVTH573

SOIC − DW

Tape and reel SN74LVTH573DWR LVTH573

SOP − NS Tape and reel SN74LVTH573NSR LVTH573

−40°C to 85°C

SSOP − DB Tape and reel SN74LVTH573DBR LXH573

40 C

85 C

TSSOP PW

Tube SN74LVTH573PW

LXH573

TSSOP − PW

Tape and reel SN74LVTH573PWR

LXH573

VFBGA − GQN

Tape and reel

SN74LVTH573GQNR

LXH573

VFBGA − ZQN (Pb-free)

Tape and reel

SN74LVTH573ZQNR

LXH573

CDIP − J Tube SNJ54LVTH573J SNJ54LVTH573J

−55°C to 125°C

CFP − W Tube SNJ54LVTH573W SNJ54LVTH573W

LCCC − FK Tube SNJ54LVTH573FK SNJ54LVTH573FK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available

at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

Summary of content (24 pages)

PAGE 1
SN54LVTH573, SN74LVTH573 3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS687H − MAY 1997 − REVISED SEPTEMBER 2003 19 2 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q LE 1D 2D 3D 4D 5D 6D 7D 8D 20 2D 1D OE VCC 1 SN54LVTH573 . . .
PAGE 2
SN54LVTH573, SN74LVTH573 3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS687H − MAY 1997 − REVISED SEPTEMBER 2003 description/ordering information (continued) These octal latches are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. The eight latches of the ’LVTH573 devices are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs.
PAGE 3
SN54LVTH573, SN74LVTH573 3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS687H − MAY 1997 − REVISED SEPTEMBER 2003 logic diagram (positive logic) OE LE 1 11 C1 1D 2 19 1D 1Q To Seven Other Channels Pin numbers shown are for the DB, DW, FK, J, NS, PW, RGY, and W packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 4
SN54LVTH573, SN74LVTH573 3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS687H − MAY 1997 − REVISED SEPTEMBER 2003 recommended operating conditions (see Note 5) SN54LVTH573 SN74LVTH573 MIN MAX MIN MAX 2.7 3.6 2.7 3.6 UNIT VCC Supply voltage VIH High-level input voltage VIL Low-level input voltage 0.8 0.8 VI Input voltage 5.5 5.
PAGE 5
SN54LVTH573, SN74LVTH573 3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS687H − MAY 1997 − REVISED SEPTEMBER 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54LVTH573 PARAMETER VIK VOH TEST CONDITIONS VCC = 2.7 V, II = −18 mA VCC = 2.7 V to 3.6 V, IOH = −100 μA VCC = 2.7 V, IOH = −8 mA VCC = 3 V VCC = 2 2.7 7V VOL VCC = 3 V MIN TYP† SN74LVTH573 MAX MIN TYP† −1.2 IOH = −24 mA −1.2 VCC−0.2 VCC−0.2 2.4 2.
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SN54LVTH573, SN74LVTH573 3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS687H − MAY 1997 − REVISED SEPTEMBER 2003 timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) SN54LVTH573 VCC = 3.3 V ± 0.3 V MIN MAX SN74LVTH573 VCC = 3.3 V ± 0.3 V VCC = 2.7 V MIN MAX MIN MAX VCC = 2.7 V MIN UNIT MAX tw Pulse duration, LE high 3 3 3 3 ns tsu Setup time, data before LE↓ 0.7 0.6 0.7 0.
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SN54LVTH573, SN74LVTH573 3.3-V ABT OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS SCBS687H − MAY 1997 − REVISED SEPTEMBER 2003 PARAMETER MEASUREMENT INFORMATION 6V 500 Ω From Output Under Test S1 Open GND CL = 50 pF (see Note A) 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 6V GND 2.7 V LOAD CIRCUIT Timing Input 1.5 V 0V tw tsu th 2.7 V 1.5 V Input 1.5 V 2.7 V Data Input 1.5 V 1.5 V 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES 2.7 V 1.
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 9
PACKAGE OPTION ADDENDUM www.ti.
PAGE 10
PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
PAGE 11
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74LVTH573DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1 SN74LVTH573DWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 SN74LVTH573NSR SO NS 20 2000 330.0 24.4 8.2 13.0 2.5 12.0 24.
PAGE 12
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVTH573DBR SN74LVTH573DWR SSOP DB 20 2000 367.0 367.0 38.0 SOIC DW 20 2000 367.0 367.0 45.0 SN74LVTH573NSR SO NS 20 2000 367.0 367.0 45.0 SN74LVTH573PWR TSSOP PW 20 2000 367.0 367.0 38.0 SN74LVTH573RGYR VQFN RGY 20 3000 367.0 367.0 35.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.