Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Inverter Inverter 74LVU SOIC 14

 

 

SCES130L − MARCH 1998 − REVISED DECEMBER 2004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D 2-V to 5.5-V V

Operation

D Unbuffered Outputs

D Max t

of 6.5 ns at 5 V

D Typical V

OLP

(Output Ground Bounce)

<0.8 V at V

= 3.3 V, T

= 25°C

D Typical V

OHV

(Output V

Undershoot)

>2.3 V at V

= 3.3 V, T

= 25°C

D Support Mixed-Mode Voltage Operation on

All Ports

D Latch-Up Performance Exceeds 250 mA Per

JESD 17

D ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

− 1000-V Charged-Device Model (C101)

GND

SN54LVU04A ...J OR W PACKAGE

SN74LVU04A . . . D, DB, DGV, NS,

OR PW PACKAGE

(TOP VIEW)

3212019

910111213

GND

SN54LVU04A . . . FK PACKAGE

(TOP VIEW)

NC − No internal connection

SN74LVU04A . . . RGY PACKAGE

(TOP VIEW)

114

GND

description/ordering information

These hex inverters are designed for 2-V to 5.5-V V

operation.

The ’LVU04A devices contain six independent inverters with unbuffered outputs. These devices perform the

Boolean function Y = A

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

QFN − RGY Reel of 1000 SN74LVU04ARGYR LVU04A

SOIC − D

Tube of 50 SN74LVU04AD

LVU04A

SOIC − D

Reel of 2500 SN74LVU04ADR

LVU04A

SOP − NS Reel of 2000 SN74LVU04ANSR LVU04A

−40°C to 85°C

SSOP − DB Reel of 2000 SN74LVU04ADBR LU04A

−40 C to 85 C

Tube of 90 SN74LVU04APW

TSSOP − PW

Reel of 2000 SN74LVU04APWR

LU04A

TSSOP − PW

Reel of 250 SN74LVU04APWT

LU04A

TVSOP − DGV Reel of 2000 SN74LVU04ADGVR LU04A

CDIP − J Tube of 25 SNJ54LVU04AJ SNJ54LVU04AJ

−55°C to 125°C

CFP − W Tube of 150 SNJ54LVU04AW SNJ54LVU04AW

−55 C to 125 C

LCCC − FK Tube of 85 SNJ54LVU04AFK SNJ54LVU04AFK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Summary of content (18 pages)

PAGE 1
SCES130L − MARCH 1998 − REVISED DECEMBER 2004 SN54LVU04A . . . J OR W PACKAGE SN74LVU04A . . . D, DB, DGV, NS, OR PW PACKAGE (TOP VIEW) 13 3 12 4 11 5 10 6 7 9 8 SN54LVU04A . . . FK PACKAGE (TOP VIEW) VCC 6A 6Y 5A 5Y 4A 4Y 1Y 2A 2Y 3A 3Y 1 14 1Y 1A NC VCC 6A SN74LVU04A . . .
PAGE 2
SCES130L − MARCH 1998 − REVISED DECEMBER 2004 FUNCTION TABLE (each inverter) INPUT A OUTPUT Y H L L H logic diagram, each inverter (positive logic) A Y absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . .
PAGE 3
SCES130L − MARCH 1998 − REVISED DECEMBER 2004 recommended operating conditions (see Note 5) SN54LVU04A VCC VIH High-level input voltage VIL Low-level input voltage VI VO Input voltage IOH IOL MIN MAX 2 5.5 Supply voltage VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 1.7 MAX 2 5.5 VCC × 0.8 VCC × 0.8 VCC × 0.8 VCC × 0.8 VCC × 0.8 VCC × 0.8 V 0.3 VCC × 0.2 VCC × 0.2 VCC × 0.2 5.5 0 Output voltage UNIT V 0.3 VCC × 0.
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SCES130L − MARCH 1998 − REVISED DECEMBER 2004 switching characteristics over recommended operating VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) tpd A Y LOAD CAPACITANCE MIN free-air TA = 25°C TYP MAX temperature SN54LVU04A range, SN74LVU04A MIN MAX MIN MAX CL = 15 pF 3.2* 10.9* 1* 14* 1 14 CL = 50 pF 6.6 13.
PAGE 5
SCES130L − MARCH 1998 − REVISED DECEMBER 2004 PARAMETER MEASUREMENT INFORMATION From Output Under Test From Output Under Test Test Point RL = 1 kΩ VCC Open S1 TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input 0V tw tsu VCC 50% VCC Input 50% VCC th VCC 50% VCC Data Input 50% VCC 0V 0V VOL
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 21-Mar-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PAGE 9
PACKAGE MATERIALS INFORMATION www.ti.com 17-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SN74LVU04ADBR SSOP SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) DB 14 2000 330.0 16.4 8.2 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.6 2.5 12.0 16.0 Q1 SN74LVU04ADR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 SN74LVU04ANSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.
PAGE 10
PACKAGE MATERIALS INFORMATION www.ti.com 17-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LVU04ADBR SSOP DB 14 2000 367.0 367.0 38.0 SN74LVU04ADR SOIC D 14 2500 367.0 367.0 38.0 SN74LVU04ANSR SO NS 14 2000 367.0 367.0 38.0 SN74LVU04APWR TSSOP PW 14 2000 367.0 367.0 35.0 SN74LVU04APWT TSSOP PW 14 250 367.0 367.0 35.
PAGE 11
MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°– 8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.