Datasheet

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SN74S1051

12-BIT SCHOTTKY BARRIER DIODE

BUS-TERMINATION ARRAY

SDLS018B – SEPTEMBER 1990 – REVISED MARCH 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Designed to Reduce Reflection Noise

Repetitive Peak Forward Current to 200 mA

12-Bit Array Structure Suited for

Bus-Oriented Systems

description/ordering information

This Schottky barrier diode bus-termination array

is designed to reduce reflection noise on memory

bus lines. This device consists of a 12-bit

high-speed Schottky diode array suitable for

clamping to V

and/or GND.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP – N Tube SN74S1051N SN74S1051N

SOIC D

Tube SN74S1051D

S1051

0°C to 70°C

SOIC

–

Tape and reel SN74S1051DR

S1051

SOP – NS Tape and reel SN74S1051NSR 74S1051

TSSOP – PW Tape and reel SN74S1051PWR S1051

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

schematic diagrams

D01

D02

D03

D04

D05

D06

D07

D08

D09

D10

D11

D12

GND

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

D, N, NS, OR PW PACKAGE

(TOP VIEW)

D01

D02

D03

D04

D05

D06

GND

D12

D11

D10

D09

D08

D07

GND

Summary of content (17 pages)

PAGE 1
SN74S1051 12-BIT SCHOTTKY BARRIER DIODE BUS-TERMINATION ARRAY SDLS018B – SEPTEMBER 1990 – REVISED MARCH 2003 D D D D, N, NS, OR PW PACKAGE (TOP VIEW) Designed to Reduce Reflection Noise Repetitive Peak Forward Current to 200 mA 12-Bit Array Structure Suited for Bus-Oriented Systems VCC D01 D02 D03 D04 D05 D06 GND description/ordering information This Schottky barrier diode bus-termination array is designed to reduce reflection noise on memory bus lines.
PAGE 2
SN74S1051 12-BIT SCHOTTKY BARRIER DIODE BUS-TERMINATION ARRAY SDLS018B – SEPTEMBER 1990 – REVISED MARCH 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Steady-state reverse voltage, VR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Continuous forward current, IF: Any D terminal from GND or to VCC . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 3
SN74S1051 12-BIT SCHOTTKY BARRIER DIODE BUS-TERMINATION ARRAY SDLS018B – SEPTEMBER 1990 – REVISED MARCH 2003 PARAMETER MEASUREMENT INFORMATION 50 Ω (See Note A) 450 Ω Pulse Generator Sampling Oscilloscope (See Note B) DUT 90% VFM VF Output Waveform (See Note B) Input Pulse (See Note A) 10% tr NOTES: A. The input pulse is supplied by a pulse generator having the following characteristics: tr = 20 ns, ZO = 50 Ω, freq = 500 Hz, duty cycle = 1%. B.
PAGE 4
SN74S1051 12-BIT SCHOTTKY BARRIER DIODE BUS-TERMINATION ARRAY SDLS018B – SEPTEMBER 1990 – REVISED MARCH 2003 APPLICATION INFORMATION Large negative transients at the inputs of memory devices (DRAMs, SRAMs, EPROMs, etc.) or on the CLOCK lines of many clocked devices can result in improper operation of the devices. The SN74S1051 diode termination array helps suppress negative transients caused by transmission-line reflections, crosstalk, and switching noise.
PAGE 5
SN74S1051 12-BIT SCHOTTKY BARRIER DIODE BUS-TERMINATION ARRAY SDLS018B – SEPTEMBER 1990 – REVISED MARCH 2003 DIODE FORWARD CURRENT vs DIODE FORWARD VOLTAGE 100 TA = 25°C 90 I I – Forward Current – mA 80 70 60 50 40 30 20 10 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 VI – Forward Voltage – V Figure 4.
PAGE 6
SN74S1051 12-BIT SCHOTTKY BARRIER DIODE BUS-TERMINATION ARRAY SDLS018B – SEPTEMBER 1990 – REVISED MARCH 2003 APPLICATION INFORMATION ZO = 50 Ω Length = 36 in. Figure 5. Diode Test Setup 56.500 ns 31.500 ns End-ofLine Without Diode 81.500 ns End-of-Line With Diode Vmarker 1 Vmarker 2 Ch 2 Timebase Memory 1 Vmarker 1 Vmarker 2 Offset = 0.000 V Delay = 56.500 ns Delta V = –2.293 V = 1.880 V/div = 5.00 ns/V = 1.880 V/div = –1.353 V = –3.647 V Figure 6.
PAGE 7
PACKAGE OPTION ADDENDUM www.ti.
PAGE 8
PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production.
PAGE 9
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74S1051DR Package Package Pins Type Drawing SOIC SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SN74S1051NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 SN74S1051PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.
PAGE 10
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74S1051DR SOIC D 16 2500 333.2 345.9 28.6 SN74S1051NSR SO NS 16 2000 367.0 367.0 38.0 SN74S1051PWR TSSOP PW 16 2000 367.0 367.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.