Datasheet

SN74S1053
16-BIT SCHOTTKY BARRIER DIODE
BUS-TERMINATION ARRAY
SDLS017A – SEPTEMBER 1990 – REVISED AUGUST 1997
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Designed to Reduce Reflection Noise
Repetitive Peak Forward Current to 200 mA
16-Bit Array Structure Suited for
Bus-Oriented Systems
Package Options Include Plastic
Small-Outline Packages and Standard
Plastic 300-mil DIPs
description
This Schottky barrier diode bus-termination array
is designed to reduce reflection noise on memory
bus lines. This device consists of a 16-bit
high-speed Schottky diode array suitable for
clamping to V
CC
and/or GND.
The SN74S1053 is characterized for operation
from 0°C to 70°C.
schematic diagrams
D01
2
D02
3
D03
4
D04
5
D05
6
D06
7
D07
8
D08
9
D09
12
D10
13
D11
14
D12
15
D13
16
D14
17
D15
18
D16
19
10
GND
11
GND
V
CC
1
V
CC
20
Copyright  1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
D01
D02
D03
D04
D05
D06
D07
D08
GND
V
CC
D16
D15
D14
D13
D12
D11
D10
D09
GND
DW OR N PACKAGE
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