Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Custom logic Voltage limiter TVSOP 48



  

SCDS087G − APRIL 1999 − REVISED APRIL 2005

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Member of the Texas Instruments

Widebus Family

D Designed to Be Used in Voltage-Limiting

Applications

D 6.5-Ω On-State Connection Between Ports

A and B

D Flow-Through Pinout for Ease of Printed

Circuit Board Trace Routing

D Direct Interface With GTL+ Levels

D ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

− 1000-V Charged-Device Model (C101)

description/ordering information

The SN74TVC16222A provides 23 parallel

NMOS pass transistors with a common gate. The

low on-state resistance of the switch allows

connections to be made with minimal propagation

delay.

The device can be used as a 22-bit switch, with the

gates cascaded together to a reference transistor.

The low-voltage side of each pass transistor is

limited to a voltage set by the reference transistor.

This is done to protect components with inputs

that are sensitive to high-state voltage-level

overshoots. (See Application Information in this

data sheet.)

All of the transistors in the TVC array have the same electrical characteristics; therefore, any one of them can

be used as the reference transistor. Because, within the device, the characteristics from transistor to transistor

are equal, the maximum output high-state voltage (V

) is approximately the reference voltage (V

REF

), with

minimal deviation from one output to another. This is a benefit of the TVC solution over discrete devices.

Because the fabrication of the transistors is symmetrical, either port connection of each bit can be used as the

low-voltage side, and the I/O signals are bidirectional through each FET.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

SSOP − DL

Tube SN74TVC16222DL

TVC16222A

−40°C to 85°C

SSOP − DL

Tape and reel SN74TVC16222DLR

TVC16222A

−40°C to 85°C

TSSOP − DGG Tape and reel SN74TVC16222DGGR TVC16222A

TVSOP − DGV Tape and reel SN74TVC16222DGVR TW222A

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus and TI are trademarks of Texas Instruments.

DGG, DGV, OR DL PACKAGE

(TOP VIEW)

GND

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

GATE

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

   ! "#$ !  %#&'" ($)

(#"! "  !%$""! %$ *$ $!  $+! !#$!

!(( ,-) (#" %"$!!. ($!  $"$!!'- "'#($

$!.  '' %$$!)

Summary of content (17 pages)

PAGE 1
SCDS087G − APRIL 1999 − REVISED APRIL 2005 D Member of the Texas Instruments D D D D D DGG, DGV, OR DL PACKAGE (TOP VIEW) Widebus Family Designed to Be Used in Voltage-Limiting Applications 6.
PAGE 2
SCDS087G − APRIL 1999 − REVISED APRIL 2005 simplified schematic GATE B1 B2 B3 B4 B23 48 47 46 45 44 25 1 2 3 4 5 24 GND A1 A2 A3 A4 A23 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input/output voltage range, VI/O (see Note 1) . . . . . . . . . . . . . . . . . .
PAGE 3
SCDS087G − APRIL 1999 − REVISED APRIL 2005 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VIK VOL Ci(GATE) Cio(off) Cio(on) ron‡ TEST CONDITIONS VBIAS = 0, IREF = 5 mA, VDPU = 2.625 V, II = −18 mA VREF = 1.365 V, RDPU = 150 Ω MIN TYP† VS = 0.175 V, See Figure 2 VI = 3 V or 0 VO = 3 V or 0 MAX UNIT −1.2 V 350 mV 73 VO = 3 V or 0 IREF = 5 mA, VDPU = 2.625 V, VREF = 1.
PAGE 4
SCDS087G − APRIL 1999 − REVISED APRIL 2005 PARAMETER MEASUREMENT INFORMATION VDPU 3.3 V Motherboard Interface 200 kΩ † GATE 48 RDPU = 150 Ω RDPU = 150 Ω † † RDPU = 150 Ω † RDPU = 150 Ω B1 (VBIAS) 47 B2 46 B3 45 B4 44 B23 25 2 A1 (VREF) 3 A2 (VS) 4 A3 (VS) 5 A4 (VS) 24 A23 (VS) ‡ TVC16222A 1 § § § § Open-Drain Test Interface TESTER CALIBRATION SETUP (see Note C) GATE 2.5 V Input Tester 1.25 V 1.
PAGE 5
SCDS087G − APRIL 1999 − REVISED APRIL 2005 APPLICATION INFORMATION TVC background information In personal computer (PC) architecture, there are industry-accepted bus standards. These standards define, among other things, the I/O voltage levels at which the bus communicates. Examples include the GTL+ host bus, the AGP graphics port, and the PCI local bus. In new designs, the system components must communicate with existing bus infrastructure.
PAGE 6
SCDS087G − APRIL 1999 − REVISED APRIL 2005 APPLICATION INFORMATION TVC voltage-limiting application For the voltage-limiting configuration, the common GATE input must be connected to one side (A or B) of any one of the transistors (see Figure 3). This connection determines the VBIAS input of the reference transistor. The VBIAS input is connected through a pullup resistor (typically 200 kΩ ) to the VDD supply. A filter capacitor on VBIAS is recommended.
PAGE 7
SCDS087G − APRIL 1999 − REVISED APRIL 2005 APPLICATION INFORMATION electrical characteristics The electrical characteristics of the NMOS transistors used in the TVC devices are illustrated by TI SPICE simulations. Figure 4 shows the test configuration for the TI SPICE simulations. The results, shown in Figures 5 and 6, show the current through a pass transistor versus the voltage at the source for different reference voltages.
PAGE 8
SCDS087G − APRIL 1999 − REVISED APRIL 2005 I PASS − Pass Current − mA APPLICATION INFORMATION VREF = 1 V VDDREF = 3.3 V RDREF = 200 kΩ RDPASS = 150 Ω VDDPASS = 3.3 V −2 −4 −6 −8 −10 −12 −14 −16 Weak Nominal Strong −18 −20 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 I PASS − Pass Current − mA VSPASS − Low Reference Voltage − V −2 VREF = 1.5 V VDDREF = 3.3 V RDREF = 200 kΩ RDPASS = 150 Ω VDDPASS = 3.3 V −4 −6 −8 −10 −12 −14 −16 Weak Nominal Strong −18 −20 0.4 0.8 1.2 1.
PAGE 9
SCDS087G − APRIL 1999 − REVISED APRIL 2005 I PASS − Pass Current − mA APPLICATION INFORMATION VREF = 2.5 V VDDREF = 3.3 V RDREF = 200 kΩ RDPASS = 150 Ω VDDPASS = 3.3 V −2 −4 −6 −8 −10 −12 −14 −16 Weak Nominal Strong −18 −20 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 I PASS − Pass Current − mA VSPASS − Low Reference Voltage − V VREF = 2.5 V VDDREF = 4 V RDREF = 200 kΩ RDPASS = 150 Ω VDDPASS = 3.3 V −2 −4 −6 −8 −10 −12 −14 −16 Weak Nominal Strong −18 −20 0.4 0.8 1.2 1.6 2.
PAGE 10
SCDS087G − APRIL 1999 − REVISED APRIL 2005 APPLICATION INFORMATION features and benefits The TVC family has several features that benefit a system designer when implementing a sensitive-I/O-protection solution. Table 1 lists these features and their associated benefits. Table 1. Features and Benefits FEATURES BENEFITS Any FET can be used as the reference transistor.
PAGE 11
PACKAGE OPTION ADDENDUM www.ti.
PAGE 12
PACKAGE MATERIALS INFORMATION www.ti.com 11-Aug-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 8.6 15.8 1.8 12.0 24.0 Q1 SN74TVC16222ADGGR TSSOP DGG 48 2000 330.0 24.4 SN74TVC16222ADGVR TVSOP DGV 48 2000 330.0 16.4 7.1 10.2 1.6 12.0 16.0 Q1 SN74TVC16222ADLR SSOP DL 48 1000 330.0 32.4 11.35 16.2 3.1 16.0 32.
PAGE 13
PACKAGE MATERIALS INFORMATION www.ti.com 11-Aug-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74TVC16222ADGGR TSSOP DGG 48 2000 346.0 346.0 41.0 SN74TVC16222ADGVR TVSOP DGV 48 2000 346.0 346.0 33.0 SN74TVC16222ADLR SSOP DL 48 1000 346.0 346.0 49.
PAGE 14
MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
PAGE 15
MECHANICAL DATA MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0.025 (0,635) 0.0135 (0,343) 0.008 (0,203) 48 0.005 (0,13) M 25 0.010 (0,25) 0.005 (0,13) 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 0°–ā8° 24 0.040 (1,02) A 0.020 (0,51) Seating Plane 0.110 (2,79) MAX 0.004 (0,10) 0.008 (0,20) MIN PINS ** 28 48 56 A MAX 0.380 (9,65) 0.630 (16,00) 0.730 (18,54) A MIN 0.370 (9,40) 0.
PAGE 16
MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°– 8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters.
PAGE 17
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.