Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - FIFO memory Synchronous Unidirectional Depth, Width LQFP 80

SN74V263, SN74V273, SN74V283, SN74V293

8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18

3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES

SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Choice of Memory Organizations

– SN74V263 – 8192 × 18/16384 × 9

– SN74V273 – 16384 × 18/32768 × 9

– SN74V283 – 32768 × 18/65536 × 9

– SN74V293 – 65536 × 18/131072 × 9

166-MHz Operation

6-ns Read/Write Cycle Time

User-Selectable Input and Output Port Bus

Sizing

– ×9 in to ×9 out

– ×9 in to ×18 out

– ×18 in to ×9 out

– ×18 in to ×18 out

Big-Endian/Little-Endian User-Selectable

Byte Representation

5-V-Tolerant Inputs

Fixed, Low First-Word Latency

Zero-Latency Retransmit

Master Reset Clears Entire FIFO

Partial Reset Clears Data, but Retains

Programmable Settings

Empty, Full, and Half-Full Flags Signal FIFO

Status

Programmable Almost-Empty and

Almost-Full Flags; Each Flag Can Default to

One of Eight Preselected Offsets

Selectable Synchronous/Asynchronous

Timing Modes for Almost-Empty and

Almost-Full Flags

Program Programmable Flags by Either

Serial or Parallel Means

Select Standard Timing (Using EF and FF

Flags) or First-Word Fall-Through (FWFT)

Timing (Using OR

and IR Flags)

Output Enable Puts Data Outputs in

High-Impedance State

Easily Expandable in Depth and Width

Independent Read and Write Clocks Permit

Reading and Writing Simultaneously

High-Performance Submicron CMOS

Technology

Glueless Interface With ’C6x DSPs

Available in 80-Pin Thin Quad Flat Pack

(TQFP) and 100-Pin Ball Grid Array (BGA)

Packages

description

The SN74V263, SN74V273, SN74V283, and SN74V293 are exceptionally deep, high-speed, CMOS first-in

first-out (FIFO) memories with clocked read and write controls and a flexible bus-matching ×9/×18 data flow.

There is flexible ×9/×18 bus matching on both read and write ports.

The period required by the retransmit operation is fixed and short.

The first-word data-latency period, from the time the first word is written to an empty FIFO to the time it can be

read, is fixed and short.

These FIFOs are particularly appropriate for network, video, telecommunications, data communications, and

other applications that need to buffer large amounts of data and match buses of unequal sizes.

Each FIFO has a data input port (Dn) and a data output port (Qn), both of which can assume either an 18-bit

or 9-bit width, as determined by the state of external control pins’ input width (IW) and output width (OW) during

the master-reset cycle.

The input port is controlled by write-clock (WCLK) and write-enable (WEN

) inputs. Data is written into the FIFO

on every rising edge of WCLK when WEN

is asserted. The output port is controlled by read-clock (RCLK) and

read-enable (REN

) inputs. Data is read from the FIFO on every rising edge of RCLK when REN is asserted.

An output-enable (OE

) input is provided for 3-state control of the outputs.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Summary of content (52 pages)

PAGE 1
SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.
PAGE 2
SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.
PAGE 3
SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.
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SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.
PAGE 5
SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 description (continued) Also, the timing modes of PAE and PAF outputs can be selected. Timing modes can be set to be either asynchronous or synchronous for PAE and PAF. If the asynchronous PAE/PAF configuration is selected, PAE is asserted low on the low-to-high transition of RCLK.
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SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.
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SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 Table 1. Bus-Matching Configuration Modes IW OW WRITE PORT WIDTH READ PORT WIDTH L L ×18 ×18 L H ×18 ×9 H L ×9 ×18 H H ×9 ×9 Terminal Functions TERMINAL NAME I/O DESCRIPTION BE I Big endian/little endian. During master reset, a low on BE selects big-endian operation.
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SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 Terminal Functions (Continued) TERMINAL NAME I/O DESCRIPTION I Programmable-flag mode. During master reset, a low on PFM selects asynchronous programmable-flag timing mode. A high on PFM selects synchronous programmable-flag timing mode. PRS I Partial reset.
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SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 partial reset (PRS) A partial reset is accomplished when the PRS input is taken to a low state. As in the case of the master reset, the internal read and write pointers are set to the first location of the RAM array, PAE goes low, PAF goes high, and HF goes high.
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SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 first-word fall-through/serial in (FWFT/SI) FWFT/SI is a dual-purpose pin. During master reset, the state of the FWFT/SI input determines whether the device operates in FWFT mode or standard mode. If, at the time of master reset, FWFT/SI is high, FWFT mode is selected.
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SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 read enable (REN) When REN is low, data is loaded from the RAM array into the output register on the rising edge of every RCLK cycle, if the device is not empty. When REN is high, the output register holds the previous data and no new data is loaded into the output register. The data outputs Q0–Qn maintain the previous data value.
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SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 programmable-flag mode (PFM) During master reset, a low on PFM selects asynchronous programmable-flag timing mode. A high on PFM selects synchronous programmable-flag timing mode. If asynchronous PAF/PAE configuration is selected (PFM low during MRS), PAE is asserted low on the low-to-high transition of RCLK.
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SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 empty flag/output ready (EF/OR) EF/OR is a dual-purpose pin. In FWFT mode, the OR function is selected. OR goes low at the same time that the first word written to an empty FIFO appears valid on the outputs. OR stays low after the RCLK low-to-high transition that shifts the last word from the FIFO memory to the outputs.
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SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 half-full flag (HF) The HF output indicates a half-full FIFO. The rising WCLK edge that fills the FIFO beyond half-full sets HF low. The flag remains low until the difference between the write and read pointers becomes less than or equal to half of the total depth of the device.
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SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Terminal voltage range with respect to GND, VTERM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.5 V Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 timing requirements over recommended ranges of supply voltage and operating free-air temperature (see Figure 2 through Figure 22)† SN74V263-6 SN74V273-6 SN74V283-6 SN74V293-6 MIN MAX SN74V263-7.5 SN74V273-7.5 SN74V283-7.5 SN74V293-7.
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SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 PARAMETER MEASUREMENT INFORMATION VCC/2 AC TEST CONDITIONS Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load for tCLK = 10 ns, 15 ns Output Load for tCLK = 7.5 ns 50 Ω GND to 3.0 V 3 ns (see Note A) 1.5 V 1.5 V See A See B and C ZO = 50 Ω I/O B. AC TEST LOAD FOR 6- AND 7.
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SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 functional description timing modes: FWFT mode vs standard mode The SN74V263, SN74V273, SN74V283, and SN74V293 support two different timing modes of operation: FWFT or standard. The selection of the mode is determined during master reset by the state of FWFT/SI. If, at the time of master reset, FWFT/SI is high, then FWFT mode is selected.
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SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 FWFT mode (continued) When configured in FWFT mode, the OR flag output is triple register buffered, and the IR flag output is double register buffered. Timing diagrams for FWFT mode can be found in Figures 9, 10, and 12. standard mode In this mode, status flags FF, PAF, HF, PAE, and EF operate as outlined in Table 3.
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SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 Table 2.
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SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 Table 3.
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SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.
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SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.
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SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 serial programming mode If the serial programming mode has been selected as described previously, programming of PAE and PAF values can be achieved by using a combination of the LD, SEN, WCLK, and SI inputs.
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SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 parallel programming mode (continued) Writing offsets in parallel employs a dedicated write offset register pointer. Reading offsets employs a dedicated read offset register pointer. The two pointers operate independently; however, a read and a write should not be performed simultaneously to the offset registers.
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SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 retransmit operation The retransmit operation allows data that has already been read to be accessed again. There are two modes of retransmit operation: normal latency and zero latency. There are two stages to retransmit. The first stage is a setup procedure that resets the read pointer to the first location of memory.
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SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.
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SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.
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SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 tRS PRS tRSS tRSR tRSS tRSR REN WEN tRSS RT tRSS SEN tRSF If FWFT = High, OR = High EF/OR If FWFT = Low, EF = Low tRSF If FWFT = Low, FF = High FF/IR If FWFT = High, IR = Low tRSF PAE tRSF PAF, HF tRSF OE = High Q0–Qn OE = Low Figure 6.
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SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 tCLK No Write tCLKH WCLK No Write tCLKH 2 1 tsk1 (see Note A) D0–Dn 1 tDS tDH 2 tsk1 (see Note A) Dx tDS tDH Dx + 1 tWFF tWFF tWFF tWFF FF WEN RCLK tENS tENS tENH tENH REN tA Q0–Qn Data In Output Register tA Data Read Next Data Read NOTES: A.
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SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 tCLKH RCLK 1 tENS tCLK tCLKL 2 tENS tENH No Operation REN tENH tENS tENH No Operation tref tref tref EF tA tA Last Word Q0–Qn Last Word tOLZ tOHZ tA D0 D1 tOLZ tOE OE tsk1 (see Note A) WCLK tENS tENH tENS tENH WEN tDS D0–Dn tDH D0 tDS tDH D1 NOTES: A.
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ÎÎ ÎÎÎÎÎÎ Î Î Î Î ÎÎÎÎÎÎ Î Î Î Î Î Î ÎÎÎ ÎÎ ÎÎÎÎÎÎ Î Î Î Î ÎÎÎÎÎÎ Î Î Î Î Î Î ÎÎÎ tDH tDS D0–D17 W1 W2 tDS W3 W[n+2] W4 tsk1 (see Note A) RCLK 1 2 W[n+3] tDS W[n+4] W D – 1+ 1 2 W D – 1+ 2 2 W tDS D – 1+ 3 2 W[D-m-2] W[D-m-1] W[D-m] tENH W[D-m+1] W[D-m+2] W[D] W[D+1] tsk2 (see Note B) 3 1 2 REN tA Q0–Q17 W1 Data in Output Register OR × POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 tREF × WEN × 2 × 1 SN74V263, SN74V273, SN74V283, SN74V293 8192 18, 16384 18, 3276
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WCLK 1 tENH 2 tsk2 (see Note B) tsk1 (see Note A) tENS WEN ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ tDH tDS D0–D17 WD RCLK 1 2 tENS tENS REN OE tA tOHZ Q0–Q17 W1 tA tA tA tA tA W1 W2 W3 Wm+2 W[m+3] W[m+4] W D – 1+ 1 2 W D – 1+ 2 2 W[D-n-1] W[D-n] W[D-n+1] W[D-n+2] W[D-1] WD tREF tWFF IR NOTES: A. tsk1 is the minimum time between a rising RCLK edge and a rising WCLK edge to ensure that IR goes low after one WCLK cycle + tWFF.
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SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 1 RCLK 2 tRTS tENH tENS tENH tENS REN tA Q0–Qn tA Wx Wx + 1 W1 (see Note C) tsk2 1 WCLK tA W2 (see Note C) 2 tRTS WEN tENS tENH RT tREF tREF EF tPAES PAE tHF HF tPAFS PAF Retransmit setup is complete after EF returns high; only then can a read operation begin.
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SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 tENS 3 2 1 RCLK tRTS tENH tENS tENH 4 REN tA Q0–Qn Wx Wx + 1 tA W1 (see Note D) tA tA W2 (see Note D) W3 (see Note D) W4 tsk2 1 WCLK 2 tRTS WEN tENS tENH RT tREF tREF OR tPAES PAE tHF HF tPAFS PAF NOTES: G. Retransmit setup is complete after OR returns low. H.
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SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 RCLK 2 1 3 tENS tENH REN tA Q0–Qn Wx tA Wx + 1 W1 tA tA W2 (see Note C) W3 (see Note C) tA W4 tsk2 1 WCLK 2 tRTS WEN tENH tENS RT EF (see Note A) tPAES PAE tHF HF tPAFS PAF NOTES: A. If the FIFO is empty at the point of retransmit, EF is updated based on RCLK (retransmit clock cycle).
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SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 1 RCLK 2 4 3 5 tENH tENS REN tA Q0–Qn Wx Wx + 1 tA W1 tA W2 (see Note D) W3 (see Note D) tA W4 (see Note D) tA W5 tsk2 1 WCLK 2 tRTS WEN tENS tENH RT OR tPAES PAE tHF HF tPAFS PAF NOTES: A. If the part is empty at the point of retransmit, OR is updated based on RCLK (retransmit clock cycle).
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SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 WCLK tENS tENH tENH tLDH tLDH SEN tLDS LD tDS SI tDH Bit 0 Bit x (see Note A) Bit 0 Bit x (see Note A) Empty Offset Full Offset NOTES: A. ×9 to ×9 mode: x = 13 for the SN74V263, x = 14 for the SN74V273, x = 15 for the SN74V283, and x = 16 for the SN74V293 B.
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SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 tCLK tCLKH tCLKL RCLK tLDS tLDH tLDH tENH tENH LD tENS REN tA Q0–Q16 Data In Output Register tA PAE Offset (LSB) tA PAE Offset (MSB) tA PAF Offset (LSB) PAF Offset (MSB) NOTES: A. OE = low B. This diagram is based on programming the SN74V293 ×18 bus width.
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SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 tCLKH tCLKL WCLK 1 tENS 1 2 2 tENH WEN tPAFS PAF tPAES D – m Words in FIFO (see Notes A and B) D – (m + 1) Words in FIFO (see Notes A and B) tsk2 (see Note C) D – (m + 1) Words in FIFO (see Notes A and B) RCLK tENS tENH REN NOTES: A. m = PAF offset B.
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SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 tCLKH tCLKL WCLK tENS tENH WEN n Words in FIFO (see Note B) n + 1 Words in FIFO (see Note C) n Words in FIFO (see Note B) n + 1 Words in FIFO (see Note C) PAE n Words in FIFO (see Note B) n + 1 Words in FIFO (see Note C) tsk2 (see Note D) tPAES 1 RCLK tPAES 2 1 tENS 2 tENH REN NOTES: A. B. C. D.
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SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 tCLKH tCLKL WCLK tENS tENH WEN tPAFA PAF D – (m + 1) Words in FIFO D – m Words in FIFO D – (m + 1) Words in FIFO tPAFA RCLK tENS REN NOTES: A. m = PAF offset B.
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SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 tCLKH tCLKL WCLK tENS tENH WEN PAE n Words in FIFO (see Note B) n+1 Words in FIFO (see Note C) tPAEA n + 1 Words in FIFO (see Note B) n + 2 Words in FIFO (see Note C) tPAEA n Words in FIFO (see Note B) n + 1 Words in FIFO (see Note C) RCLK tENS REN NOTES: A. B. C. D. E.
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SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 tCLKH tCLKL WCLK tENS tENH WEN tHF HF D + 1 Words in FIFO (see Note A) 2 D+1 + 1 Words in FIFO (see Note B) 2 D/2 Words in FIFO (see Note A) D/2 Words in FIFO (see Note A) D+1 Words in FIFO (see Note B) 2 tHF D + 1 Words in FIFO (see Note B) 2 RCLK tENS REN NOTES: A. In standard mode: D = maximum FIFO depth.
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SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 optional configurations width expansion configuration Word width can be increased by connecting the control signals of multiple devices. Status flags can be detected from any one device. The exceptions are the the IR and OR functions in FWFT mode and EF and FF functions in standard mode.
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SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 depth-expansion configuration (FWFT mode only) The SN74V263 can be adapted easily to applications requiring depths greater than 8192 when the ×18 input or ×18 output bus width is selected, 16384 for the SN74V273, 32768 for the SN74V283, and 65536 for the SN74V293.
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SN74V263, SN74V273, SN74V283, SN74V293 8192 × 18, 16384 × 18, 32768 × 18, 65536 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS669D – JUNE 2001 – REVISED FEBRUARY 2003 depth-expansion configuration (FWFT mode only) (continued) The transfer clock line should be tied to either WCLK or RCLK, whichever is faster. Both these actions result in data moving as quickly as possible to the end of the chain and free locations moving to the beginning of the chain.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 28-May-2009 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
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MECHANICAL DATA MPBG028B FEBRUARY 1997 – REVISED MAY 2002 GGM (S–PBGA–N100) PLASTIC BALL GRID ARRAY 10,10 SQ 9,90 7,20 TYP 0,80 0,40 K 0,80 J H G F E 0,40 D C B A A1 Corner 1 2 3 4 5 6 7 8 9 10 Bottom View 0,95 0,85 1,40 MAX Seating Plane 0,55 0,45 0,08 0,45 0,35 0,10 4145257–3/C 12/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice C. MicroStar BGA configuration.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.