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ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICs74VMEH TSSOP 48

SN74VMEH22501A

www.ti.com

SCES3620A –DECEMBER 2004–REVISED FEBRUARY 2010

8-BIT UNIVERSAL BUS TRANSCEIVER AND TWO 1-BIT BUS TRANSCEIVERS

WITH SPLIT LVTTL PORT, FEEDBACK PATH, AND 3-STATE OUTPUTS

Check for Samples: SN74VMEH22501A

FEATURES

• Member of the Texas Instruments Widebus™ • ESD Protection Exceeds JESD 22

Family

– 2000-V Human-Body Model (A114-A)

• UBT™ Transceiver Combines D-Type Latches

– 200-V Machine Model (A115-A)

and D-Type Flip-Flops for Operation in

– 1000-V Charged-Device Model (C101)

Transparent, Latched, or Clocked Modes

DGG OR DGV PACKAGE

• OEC™ Circuitry Improves Signal Integrity and

(TOP VIEW)

Reduces Electromagnetic Interference (EMI)

• Compliant With VME64, 2eVME, and 2eSST

Protocols

• Bus Transceiver Split LVTTL Port Provides a

Feedback Path for Control and Diagnostics

Monitoring

• I/O Interfaces Are 5-V Tolerant

• B-Port Outputs (–48 mA/64 mA)

• Y and A-Port Outputs (–12 mA/12 mA)

• I

off

, Power-Up 3-State, and BIAS V

Support

Live Insertion

• Bus Hold on 3A-Port Data Inputs

• 26-Ω Equivalent Series Resistor on 3A Ports

and Y Outputs

• Flow-Through Architecture Facilitates Printed

Circuit Board Layout

• Distributed V

and GND Pins Minimize

High-Speed Switching Noise

• Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

DESCRIPTION/ORDERING INFORMATION

The SN74VMEH22501A 8-bit universal bus transceiver has two integral 1-bit three-wire bus transceivers and is

designed for 3.3-V V

operation with 5-V tolerant inputs. The UBT™ transceiver allows transparent, latched, and

flip-flop modes of data transfer, and the separate LVTTL input and outputs on the bus transceivers provide a

feedback path for control and diagnostics monitoring. This device provides a high-speed interface between cards

operating at LVTTL logic levels and VME64, VME64x, or VME320

(1)

backplane topologies.

The SN74VMEH22501A is pin-for-pin capatible to the SN74VMEH22501 (TI literature number SCES357), but

operates at a wider operating temperature (−40°C to 85°C) range.

(1) VME320 is a patented backplane construction by Arizona Digital, Inc.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (31 pages)

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SN74VMEH22501A www.ti.
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SN74VMEH22501A SCES3620A – DECEMBER 2004 – REVISED FEBRUARY 2010 www.ti.com DESCRIPTION/ORDERING INFORMATION (CONTINUED) High-speed backplane operation is a direct result of the improved OEC™ circuitry and high drive that has been designed and tested into the VME64x backplane model. The B-port I/Os are optimized for driving large capacitive loads and include pseudo-ETL input thresholds (½ VCC ± 50 mV) for increased noise immunity. These specifications support the 2eVME protocols in VME64x (ANSI/VITA 1.
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SN74VMEH22501A www.ti.
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SN74VMEH22501A SCES3620A – DECEMBER 2004 – REVISED FEBRUARY 2010 www.ti.com FUNCTIONAL DESCRIPTION The SN74VMEH22501A is a high-drive (–48/64 mA), 8-bit UBT transceiver containing D-type latches and D-type flip-flops for data-path operation in transparent, latched, or flip-flop modes. Data transmission is true logic. The device is uniquely partitioned as 8-bit UBT transceivers with two integrated 1-bit three-wire bus transceivers.
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SN74VMEH22501A www.ti.com SCES3620A – DECEMBER 2004 – REVISED FEBRUARY 2010 Table 1. UBT TRANSCEIVER FUNCTION TABLE (1) INPUTS (1) (2) (3) OE LE H L OUTPUT 3B MODE Z Isolation CLKAB 3A X X X L H X B0 (2) L L L X B0 (3) L H X L L L H X H H L L ↑ L L L L ↑ H H Latched storage of 3A data True transparent Clocked storage of 3A data 3A-to-3B data flow is shown; 3B-to-3A data flow is similar, but uses CLKBA.
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SN74VMEH22501A SCES3620A – DECEMBER 2004 – REVISED FEBRUARY 2010 www.ti.com LOGIC DIAGRAM (POSITIVE LOGIC) 48 1OEAB 1 1OEBY 2 46 1A 1B 3 1Y 2OEAB 2OEBY 41 8 43 5 2A 2Y OE DIR CLKAB LE 2B 6 14 24 32 11 17 CLKBA 9 3A1 1D C1 CLK 40 3B1 1D C1 CLK To Seven Other Channels Pin numbers shown are for the DGG and DGV packages.
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SN74VMEH22501A www.ti.com SCES3620A – DECEMBER 2004 – REVISED FEBRUARY 2010 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) VCC, BIAS VCC Supply voltage range VI Input voltage range (2) VO Voltage range applied to any output in the high-impedance or power-off state VO Voltage range applied to any output in the high or low state (2) IO Output current in the low state IO Output current in the high state IIK IOK Tstg (1) (2) (3) 4.6 V –0.
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SN74VMEH22501A SCES3620A – DECEMBER 2004 – REVISED FEBRUARY 2010 www.ti.com Electrical Characteristics over recommended operating free-air temperature range for A and B ports (unless otherwise noted) PARAMETER VIK VOH VCC = 3.15 V, II = –18 mA 3A port, any B ports, and Y outputs VCC = 3.15 V to 3.45 V, IOH = –100 mA 3A port and Y outputs VCC = 3.15 V Any B port VCC = 3.15 V 3A port, any B ports, and Y outputs VCC = 3.15 V to 3.45 V, 3A port and Y outputs VCC = 3.
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SN74VMEH22501A www.ti.com SCES3620A – DECEMBER 2004 – REVISED FEBRUARY 2010 Electrical Characteristics (continued) over recommended operating free-air temperature range for A and B ports (unless otherwise noted) PARAMETER 1A and 2A inputs Ci Control inputs Co 1Y or 2Y outputs 3A port Cio Any B port MIN TYP (1) MAX TEST CONDITIONS 2.8 VI = 3.15 V or 0 VCC = 3.3 V, pF 2.6 VO = 3.15 V or 0 5.6 pF 7.9 VO = 3.3 V or 0 11 UNIT 12.
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SN74VMEH22501A SCES3620A – DECEMBER 2004 – REVISED FEBRUARY 2010 www.ti.
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SN74VMEH22501A www.ti.com SCES3620A – DECEMBER 2004 – REVISED FEBRUARY 2010 Switching Characteristics for UBT Transceiver over recommended operating conditions (unless otherwise noted) (see Figure 1 and Figure 2) PARAMETER FROM (INPUT) TO (OUTPUT) MIN TYP MAX fmax 120 tPLH 5.5 9.3 4.7 8.
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SN74VMEH22501A SCES3620A – DECEMBER 2004 – REVISED FEBRUARY 2010 www.ti.com Skew Characteristics for Bus Transceiver for specific worst-case VCC and temperature within the recommended ranges of supply voltage and operating free-air temperature (see Figure 1 and Figure 2) PARAMETER tsk(LH) tsk(HL) tsk(LH) tsk(HL) tsk(t) (1) tsk(pp) (1) FROM (INPUT) TO (OUTPUT) 1A or 2A 1B or 2B 1B or 2B 1Y or 2Y 1A or 2A 1B or 2B 1.7 1B or 2B 1Y or 2Y 1.2 1A or 2A 1B or 2B 2.8 1B or 2B 1Y or 2Y 1.
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SN74VMEH22501A www.ti.com SCES3620A – DECEMBER 2004 – REVISED FEBRUARY 2010 PARAMETER MEASUREMENT INFORMATION A PORT 6V S1 500 Ω From Output Under Test Open TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH B-to-A Skew GND CL = 50 pF (see Note A) 500 Ω S1 Open 6V GND Open LOAD CIRCUIT tw 3V 3V Timing Input 1.5 V 1.5 V Input 0V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 3V Data Input VCC/2 3V VCC/2 0V VCC/2 1.5 V 0V tPLZ tPZL 3V Input 1.
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SN74VMEH22501A SCES3620A – DECEMBER 2004 – REVISED FEBRUARY 2010 www.ti.com PARAMETER MEASUREMENT INFORMATION B PORT 6V 500 Ω From Output Under Test S1 Open TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH A-to-B Skew GND CL = 50 pF (see Note A) 500 Ω S1 Open 6V GND Open LOAD CIRCUIT tw 3V 3V Timing Input Input 1.5 V 0V 0V tsu VOLTAGE WAVEFORMS PULSE DURATION th 3V Data Input 1.5 V 3V 1.5 V 0V 1.
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SN74VMEH22501A www.ti.com SCES3620A – DECEMBER 2004 – REVISED FEBRUARY 2010 Distributed-Load Backplane Switching Characteristics The preceding switching characteristics tables show the switching characteristics of the device into the lumped load shown in the parameter measurement information (PMI) (see Figure 1 and Figure 2). All logic devices currently are tested into this type of load. However, the designer's backplane application probably is a distributed load.
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SN74VMEH22501A SCES3620A – DECEMBER 2004 – REVISED FEBRUARY 2010 www.ti.com Switching Characteristics for UBT over recommended operating conditions (unless otherwise noted) (see Figure 3) PARAMETER tPLH tPHL tPLH tPHL tPLH tPHL (1) (2) FROM (INPUT) TO (OUTPUT) 3A 3B LE 3B CLKAB 3B MIN TYP (1) MAX 6.2 8.9 5.6 9 6.1 9.1 5.6 9 6.2 9.1 5.7 9 UNIT ns ns ns tr (2) Transition time, B port (10%–90%) 9 8.6 11.4 ns tf (2) Transition time, B port (90%–10%) 8.9 9 10.
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SN74VMEH22501A www.ti.com SCES3620A – DECEMBER 2004 – REVISED FEBRUARY 2010 Switching Characteristics for Bus Transceiver Function (continued) over recommended operating conditions (unless otherwise noted) (see Figure 3) PARAMETER tPLH tPHL (1) (2) FROM (INPUT) TO (OUTPUT) 1A or 2A 1B or 2B MIN TYP (1) MAX 5.5 7.4 5.3 7.4 UNIT ns tr (2) Transition time, B port (10%–90%) 3.9 3.4 4.4 ns tf (2) Transition time, B port (90%–10%) 3.7 3.4 4.
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SN74VMEH22501A SCES3620A – DECEMBER 2004 – REVISED FEBRUARY 2010 www.ti.com Skew Characteristics for UBT for specific worst-case VCC and temperature within the recommended ranges of supply voltage and operating free-air temperature (see Figure 3) PARAMETER tsk(LH) tsk(HL) tsk(LH) tsk(HL) tsk(t) (2) tsk(pp) (1) (2) FROM (INPUT) TO (OUTPUT) 3A 3B CLKAB 3B MIN TYP (1) MAX 2 2.3 2.1 2.4 3A 3B 1 CLKAB 3B 1 3A 3B 0.2 2.5 CLKAB 3B 0.2 2.
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SN74VMEH22501A www.ti.com SCES3620A – DECEMBER 2004 – REVISED FEBRUARY 2010 6.4 6.2 Time - ns 6.0 5.8 LH 5.6 HL 5.4 5.2 5.0 Full B/P Load Minimum B/P Load PMI Lumped Load Figure 5. Characterization-laboratory data in Figure 6 and Figure 7 show the absolute ac peak output current, with different supply voltages, as the devices change output logic state. A typical nominal process is shown to demonstrate the devices' peak ac output drive capability.
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SN74VMEH22501A SCES3620A – DECEMBER 2004 – REVISED FEBRUARY 2010 www.ti.com TYPICAL CHARACTERISTICS SUPPLY CURRENT vs FREQUENCY A TO B SUPPLY CURRENT vs FREQUENCY B TO A 35 30 VCC = 3.15 V 30 25 CC(Enabled) − mA 25 VCC = 3.45 V 20 15 VCC = 3.3 V 20 VCC = 3.15 V 15 I I CC(Enabled) - mA VCC = 3.45 V VCC = 3.3 V 10 10 5 20 40 60 80 100 120 5 20 40 f - Switching Frequency - MHz Submit Documentation Feedback 80 100 120 f − Switching Frequency − MHz Figure 8. 20 60 Figure 9.
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SN74VMEH22501A www.ti.com SCES3620A – DECEMBER 2004 – REVISED FEBRUARY 2010 TYPICAL CHARACTERISTICS HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT 300 VCC = 3.15 V VOH - High-Level Output Voltage - V 250 VCC = 3.3 V 200 VCC = 3.45 V 150 100 50 0 0 10 20 30 40 50 60 70 80 90 100 IOH - High-Level Output Current - mA Figure 10. VOL vs IOL
LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 4.0 VCC = 3.45 V VOL - Low-Level Output Voltage - V 3.5 VCC = 3.3 V 3.0 2.5 VCC = 3.
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SN74VMEH22501A SCES3620A – DECEMBER 2004 – REVISED FEBRUARY 2010 www.ti.com VMEbus Summary In 1981, the VMEbus was introduced as a backplane bus architecture for industrial and commercial applications. The data-transfer protocols used to define the VMEbus came from the Motorola™ VERSA bus architecture that owed its heritage to the then recently introduced Motorola 68000 microprocessor.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com (4) 14-Feb-2013 Only one of markings shown within the brackets will appear on the physical device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information.
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PACKAGE MATERIALS INFORMATION www.ti.com 19-Feb-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN74VMEH22501ADGGR TSSOP DGG 48 2000 330.0 24.4 8.6 15.8 1.8 12.0 24.0 Q1 SN74VMEH22501ADGVR TVSOP DGV 48 2000 330.0 16.4 7.1 10.2 1.6 12.0 16.0 Q1 SN74VMEH22501AZQLR BGA MI CROSTA R JUNI OR ZQL 56 1000 330.0 16.4 4.8 7.3 1.
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PACKAGE MATERIALS INFORMATION www.ti.com 19-Feb-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74VMEH22501ADGGR TSSOP DGG 48 2000 367.0 367.0 45.0 SN74VMEH22501ADGVR TVSOP DGV 48 2000 367.0 367.0 38.0 ZQL 56 1000 336.6 336.6 28.
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MECHANICAL DATA MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE 24 PINS SHOWN 0,40 0,23 0,13 24 13 0,07 M 0,16 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 0°– 8° 1 0,75 0,50 12 A Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,08 14 16 20 24 38 48 56 A MAX 3,70 3,70 5,10 5,10 7,90 9,80 11,40 A MIN 3,50 3,50 4,90 4,90 7,70 9,60 11,20 DIM 4073251/E 08/00 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.