Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsInterface ICsInterface IC - transceivers IEEE 488 8/8 PDIP 20



    

SLLS018E − JUNE 1986 − REVISED JUNE 2004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Suitable for IEEE Standard 488-1978 (GPIB)

D 8-Channel Bidirectional Transceivers

D High-Speed Advanced Low-Power Schottky

(ALS) Circuitry

D Low Power Dissipation

. . . 46 mW Max Per Channel

D Fast Propagation Times . . . 20 ns Max

D High-Impedance pnp Inputs

D Receiver Hysteresis . . . 650 mV Typ

D Open-Collector Driver Output Option

D No Loading of Bus When Device Is

Powered Down (V

= 0)

D Power-Up/Power-Down Protection

(Glitch Free)

description/ordering information

The SN75ALS160 eight-channel general-purpose interface bus transceivers are monolithic, high-speed,

advanced low-power Schottky (ALS) devices designed for two-way data communications over single-ended

transmission lines. This device is designed to meet the requirements of IEEE Standard 488-1978. The

transceivers feature driver outputs that can be operated in either the passive-pullup or 3-state mode. If talk

enable (TE) is high, these ports have the characteristics of passive-pullup outputs when pullup enable (PE) is

low and of 3-state outputs when PE is high. Taking TE low places these ports in the high-impedance state. The

driver outputs are designed to handle loads up to 48 mA of sink current.

An active turn-off feature has been incorporated into the bus-terminating resistors so that the device exhibits

a high impedance to the bus when V

= 0. When combined with the SN75ALS161 or SN75ALS162 bus

management transceiver, the pair provides the complete 16-wire interface for the IEEE-488 bus.

The SN75ALS160 is characterized for operation from 0°C to 70°C.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP (N) Tube of 20 SN75ALS160N SN75ALS160N

0°C to 70°C

SOIC (DW)

Tube of 25 SN75ALS160DW

75ALS160

0 C to 70 C

SOIC (DW)

Reel of 2000 SN75ALS160DWR

75ALS160

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

   ! "#$ !  %#&'" ($)

(#"! "  !%$""! %$ *$ $!  $+! !#$!

!(( ,-) (#" %"$!!. ($!  $"$!!'- "'#($

$!.  '' %$$!)

GND

DW OR N PACKAGE

(TOP VIEW)

GPIB

I/O Ports

Terminal

I/O Ports

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Summary of content (18 pages)

PAGE 1
SLLS018E − JUNE 1986 − REVISED JUNE 2004 D Suitable for IEEE Standard 488-1978 (GPIB) D 8-Channel Bidirectional Transceivers D High-Speed Advanced Low-Power Schottky D D D D D D D (ALS) Circuitry Low Power Dissipation . . . 46 mW Max Per Channel Fast Propagation Times . . . 20 ns Max High-Impedance pnp Inputs Receiver Hysteresis . . .
PAGE 2
SLLS018E − JUNE 1986 − REVISED JUNE 2004 Function Tables EACH DRIVER INPUTS D TE PE OUTPUT B H H H H L H X H X L X L X L Z† Z† EACH RECEIVER INPUTS B TE PE OUTPUT D L L X L H L X H X H X Z H = high level, L = low level, X = irrelevant, Z = high-impedance state † This is the high-impedance state of a normal 3-state output modified by the internal resistors to VCC and GND.
PAGE 3
SLLS018E − JUNE 1986 − REVISED JUNE 2004 schematics of inputs and outputs EQUIVALENT OF ALL CONTROL INPUTS EQUIVALENT OF ALL INPUT/OUTPUT PORTS VCC 9 kΩ NOM R(eq) 1.7 kΩ NOM 10 kΩ NOM Input 4 kΩ NOM 4 kΩ NOM GND Input/Output Port Driver output R(eq) = 30 Ω NOM Receiver output R(eq) = 110 Ω NOM R(eq) = equivalent resistor Circuit inside dashed lines is on the driver outputs only.
PAGE 4
SLLS018E − JUNE 1986 − REVISED JUNE 2004 recommended operating conditions VCC VIH Supply voltage VIL Low-level input voltage IOH High-level output current High-level input voltage MIN NOM MAX UNIT 4.75 5 5.25 V 2 V 0.8 IOL Low-level output current TA Operating free-air temperature V Bus ports with pullups active − 5.
PAGE 5
SLLS018E − JUNE 1986 − REVISED JUNE 2004 switching characteristics at VCC = 4.75 V, 5 V, and 5.
PAGE 6
SLLS018E − JUNE 1986 − REVISED JUNE 2004 PARAMETER MEASUREMENT INFORMATION 5V PE 3V Output Generator (see Note A) D 200 Ω 3V D Input 1.5 V 1.5 V 0 B tPHL tPLH CL = 30 pF (see Note B) 50 Ω VOH 480 Ω B Output 2.2 V 1V VOH TE 3V TEST CIRCUIT VOLTAGE WAVEFORMS NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω. B.
PAGE 7
SLLS018E − JUNE 1986 − REVISED JUNE 2004 PARAMETER MEASUREMENT INFORMATION 5V 3V 200 Ω PE 3V TE Input Output S2 S1 D B CL = 15 pF (see Note B) 480 Ω 1.5 V 1.5 V 0 tPZH B Output S1 to 3 V S2 Open tPHZ 90% 2V 0.8 V tPZL Generator (see Note A) tPLZ 3.5 V B Output S1 to GND S2 Closed TE 50 Ω TEST CIRCUIT VOH 1V 0.5 V VOL VOLTAGE WAVEFORMS NOTES: A.
PAGE 8
SLLS018E − JUNE 1986 − REVISED JUNE 2004 PARAMETER MEASUREMENT INFORMATION Generator (see Note A) PE 3V 50 Ω D PE Input B Output 1.5 V 1.5 V 0 CL = 15 pF (see Note B) RL = 480 Ω ten B Output tdis 90% VOH 2V VOL ≈0.8 3V TE TEST CIRCUIT VOLTAGE WAVEFORMS NOTES: A. The input pulse is supplied by a generator having the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, tr ≤ 6 ns, tf ≤ 6 ns, ZO = 50 Ω. B.
PAGE 9
SLLS018E − JUNE 1986 − REVISED JUNE 2004 TYPICAL CHARACTERISTICS TERMINAL HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT TERMINAL LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 0.6 3.5 VOL − Low-Level Output Voltage − V VCC = 5 V TA = 25°C 3 2.5 2 1.5 1 0.5 VCC = 5 V TA = 25°C 0.5 0.4 0.3 0.2 0.
PAGE 10
SLLS018E − JUNE 1986 − REVISED JUNE 2004 TYPICAL CHARACTERISTICS BUS HIGH-LEVEL OUTPUT VOLTAGE vs BUS HIGH-LEVEL OUTPUT CURRENT BUS LOW-LEVEL OUTPUT VOLTAGE vs BUS LOW-LEVEL OUTPUT CURRENT 0.6 4 VOL− Low-Level Output Voltage − V VOH − High-Level Output Voltage − V VCC = 5 V TA = 25°C 3 2 1 VCC = 5 V TA = 25°C 0.5 0.4 0.3 0.2 0.
PAGE 11
PACKAGE OPTION ADDENDUM www.ti.
PAGE 12
PACKAGE OPTION ADDENDUM www.ti.com (4) 18-Oct-2013 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
PAGE 13
PACKAGE MATERIALS INFORMATION www.ti.com 3-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN75ALS160DWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1 SN75ALS160DWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1 SN75ALS160DWRG4 SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.
PAGE 14
PACKAGE MATERIALS INFORMATION www.ti.com 3-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN75ALS160DWR SOIC DW 20 2000 600.0 144.0 84.0 SN75ALS160DWR SOIC DW 20 2000 367.0 367.0 45.0 SN75ALS160DWRG4 SOIC DW 20 2000 367.0 367.0 45.0 SN75ALS160DWRG4 SOIC DW 20 2000 367.0 367.0 45.
PAGE 15
PAGE 16
PAGE 17
PAGE 18
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.