Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsInterface ICsInterface IC - transceivers IEEE 488 8/8 SOIC 20



    

SLLS019F − JUNE 1986 − REVISED JULY 2004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Suitable for IEEE Standard 488-1978 (GPIB)

D 8-Channel Bidirectional Transceivers

D Designed to Implement Control Bus

Interface

D Designed for Single Controller

D High-Speed Advanced Low-Power Schottky

Circuitry

D Low Power Dissipation . . . 46 mW Max Per

Channel

D Fast Propagation Times . . . 20 ns Max

D High-Impedance pnp Inputs

D Receiver Hysteresis . . . 650 mV Typ

D Bus-Terminating Resistors Provided on

Driver Outputs

D No Loading of Bus When Device Is

Powered Down (V

= 0)

D Power-Up/Power-Down Protection

(Glitch Free)

description/ordering information

The SN75ALS161 eight-channel

general-purpose interface bus transceivers are

high-speed, advanced low-power

Schottky-process devices designed to provide the

bus-management and data-transfer signals between operating units of a single-controller instrumentation

system. When combined with the SN75ALS160 octal bus transceivers, this device provides a complete 16-wire

interface for the IEEE 488 bus.

The SN75ALS161 device features eight driver-receiver pairs connected in a front-to-back configuration to form

input/output (I/O) ports at both the bus and terminal sides. The direction of data through these driver-receiver

pairs is determined by the direction-control (DC) and talk-enable (TE) signals.

The driver outputs general-purpose interface bus (GPIB I/O ports) feature active bus-terminating resistor

circuits designed to provide a high impedance to the bus when V

= 0. The drivers are designed to handle

sink-current loads up to 48 mA. Each receiver features pnp transistor inputs for high input impedance and

hysteresis of 400 mV on the commercial part, and 250 mV on the military part, minimum, for increased noise

immunity. All receivers have 3-state outputs, to present a high impedance to the terminal when disabled.

The SN75ALS161 is characterized for operation from 0°C to 70°C.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP (N) Tube of 20 SN75ALS161N SN75ALS161N

0°C to 70°C

SOIC (DW)

Tube of 25 SN75ALS161DW

75ALS161

0 C to 70 C

SOIC (DW)

Reel of 2000 SN75ALS161DWR

75ALS161

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

    !"#   $"%&! '#(

'"! !  $#!! $# )# #  #* "#

'' +,( '"! $!#- '#  #!#&, !&"'#

#-  && $##(

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

REN

IFC

NDAC

NRFD

DAV

EOI

ATN

SRQ

GND

REN

IFC

NDAC

NRFD

DAV

EOI

ATN

SRQ

GPIB

I/O Ports

Terminal

I/O Ports

NAME CLASSIDENTITY

ATN

SRQ

REN

IFC

EOI

DAV

NDAC

NRFD

CHANNEL-IDENTIFICATION TABLE

Direction Control

Talk Enable

Attention

Service Request

Remote Enable

Interface Clear

End or Identify

Data Valid

Not Data Accepted

Not Ready for Data

Control

Bus

Management

Data

Transfer

DW OR N PACKAGE

(TOP VIEW)

Summary of content (21 pages)

PAGE 1
SLLS019F − JUNE 1986 − REVISED JULY 2004 D Suitable for IEEE Standard 488-1978 (GPIB) D 8-Channel Bidirectional Transceivers D Designed to Implement Control Bus D D D D D D D D D Interface Designed for Single Controller High-Speed Advanced Low-Power Schottky Circuitry Low Power Dissipation . . . 46 mW Max Per Channel Fast Propagation Times . . . 20 ns Max High-Impedance pnp Inputs Receiver Hysteresis . . .
PAGE 2
SLLS019F − JUNE 1986 − REVISED JULY 2004 FUNCTION TABLE RECEIVE/TRANSMIT CONTROLS DC TE ATN† BUS-MANAGEMENT CHANNELS ATN† SRQ REN IFC EOI (CONTROLLED BY DC) H H H H H L L L H L L L H L L H DATA-TRANSFER CHANNELS DAV NDAC NRFD (CONTROLLED BY TE) T R T R R T R T T X R T R R X T R T T T R R R T T R R T T T T R R R R T H = high level, L = low level, R = receive, T = transmit, X = irrelevant Direction of d
PAGE 3
SLLS019F − JUNE 1986 − REVISED JULY 2004 logic diagram (positive logic) DC TE ATN EOI SRQ REN IFC DAV NDAC NRFD 11 1 13 8 14 7 12 9 19 2 18 3 15 6 17 4 16 5 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 ATN EOI SRQ REN IFC DAV NDAC NRFD 3
PAGE 4
SLLS019F − JUNE 1986 − REVISED JULY 2004 schematics of inputs and outputs EQUIVALENT OF ALL CONTROL INPUTS TYPICAL OF SRQ, NDAC, AND NRFD GPIB I/O PORT VCC 9 kΩ NOM 1.7 kΩ NOM Input 4 kΩ NOM GND Input/Output Port Circuit inside dashed lines is on the driver outputs only. TYPICAL OF ALL I/O PORTS, EXCEPT SRQ, NDAC, AND NRFD GPIB I/O PORTS R(eq) 1.
PAGE 5
SLLS019F − JUNE 1986 − REVISED JULY 2004 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 6
SLLS019F − JUNE 1986 − REVISED JULY 2004 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TEST CONDITIONS† PARAMETER VIK Vhys Input clamp voltage Hysteresis voltage (VIT+ − VIT−) II = −18 mA Bus Terminal VOH§ MIN IOH = − 800 µA, VCC = MIN High-level output voltage TYP‡ MAX UNIT −0.8 −1.5 V 0.4 0.65 2.7 3.5 TA = MIN TA = 25°C and MAX 2.7 3.5 TA = MIN 2.
PAGE 7
SLLS019F − JUNE 1986 − REVISED JULY 2004 switching characteristics over recommended operating free-air temperature range, VCC = 5 V PARAMETER tPLH Propagation delay time, low- to high-level output tPHL Propagation delay time, high- to low-level output tPLH Propagation delay time, low- to high-level output tPHL Propagation delay time, high- to low-level output FROM (INPUT) TO (OUTPUT) TEST CONDITIONS Terminal Bus CL = 30 pF, See Figure 1 Bus
PAGE 8
SLLS019F − JUNE 1986 − REVISED JULY 2004 PARAMETER MEASUREMENT INFORMATION 5V 200 Ω From (Bus) Output Under Test Test Point CL = 30 pF (see Note A) 480 Ω LOAD CIRCUIT 3V Terminal Input (see Note B) 1.5 V 1.5 V 0V tPHL tPLH Bus Output VOH 2.2 V 1V VOH VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B.
PAGE 9
SLLS019F − JUNE 1986 − REVISED JULY 2004 PARAMETER MEASUREMENT INFORMATION 4.3 V 240 Ω From (Terminal) Output Under Test Test Point CL = 30 pF (see Note A) 3 kΩ LOAD CIRCUIT 3V Bus Input (see Note B) 1.5 V 1.5 V 0V tPLH Terminal Output tPHL VOH 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B.
PAGE 10
SLLS019F − JUNE 1986 − REVISED JULY 2004 PARAMETER MEASUREMENT INFORMATION S1 5V 200 Ω From (Bus) Output Under Test Test Point CL = 15 pF (see Note A) 480 Ω LOAD CIRCUIT 3V Control Input (see Note B) 1.5 V 1.5 V 0V tPZH Bus Output S1 Open tPHZ VOH 90% 2V 0V tPLZ tPZL ≈3.5 V Bus Output S1 Closed 1V 0.5 V VOL VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B.
PAGE 11
SLLS019F − JUNE 1986 − REVISED JULY 2004 PARAMETER MEASUREMENT INFORMATION S1 4.3 V 240 Ω From (Terminal) Output Under Test Test Point CL = 15 pF (see Note A) 3 kΩ LOAD CIRCUIT 3V Control Input (see Note B) 1.5 V 1.5 V 0V tPZH Terminal Output S1 Open tPHZ 90% 1.5 V 0V tPLZ tPZL Terminal Output S1 Closed VOH ≈4 V 1V 0.7 V VOL VOLTAGE WAVEFORMS NOTES: A. CL includes probe and jig capacitance. B.
PAGE 12
SLLS019F − JUNE 1986 − REVISED JULY 2004 TYPICAL CHARACTERISTICS† TERMINAL I/O PORTS HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT TERMINAL I/O PORTS LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 0.6 VCC = 5 V TA = 25°C 3.5 VOL − Low-Level Output Voltage − V VOH − High-Level Output Voltage − V 4 3 2.5 2 1.5 1 0.5 0 VCC = 5 V TA = 25°C 0.5 0.4 0.3 0.2 0.
PAGE 13
SLLS019F − JUNE 1986 − REVISED JULY 2004 TYPICAL CHARACTERISTICS† GPIB I/O BUS HIGH-LEVEL OUTPUT VOLTAGE vs HIGH-LEVEL OUTPUT CURRENT GPIB I/O BUS LOW-LEVEL OUTPUT VOLTAGE vs LOW-LEVEL OUTPUT CURRENT 4 0.6 VOL− Low-Level Output Voltage − V VOH − High-Level Output Voltage − V VCC = 5 V TA = 25°C 3 2 1 VCC = 5 V TA = 25°C 0.5 0.4 0.3 0.2 0.
PAGE 14
PACKAGE OPTION ADDENDUM www.ti.
PAGE 15
PACKAGE OPTION ADDENDUM www.ti.
PAGE 16
PACKAGE MATERIALS INFORMATION www.ti.com 3-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN75ALS161DWR Package Package Pins Type Drawing SOIC DW 20 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 24.4 Pack Materials-Page 1 10.8 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 13.3 2.7 12.0 24.
PAGE 17
PACKAGE MATERIALS INFORMATION www.ti.com 3-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN75ALS161DWR SOIC DW 20 2000 367.0 367.0 45.
PAGE 18
PAGE 19
PAGE 20
PAGE 21
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.