Datasheet

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FEATURES

APPLICATIONS

DESCRIPTION

TYPICAL APPLICATION

Computer/Notebook/DockingStation

GPU

DP++

TMDS

DisplayPort

Enabled

MonitororHDTV

HDMI / DVI

MonitororHDTV

SN75DP122A

www.ti.com

............................................................................................................................................................................................ SLLS939 – NOVEMBER 2008

DisplayPort 1:2 Switch With Integrated TMDS Translator

• One Input Port to One of Two Output Ports – 12 kV on all High Speed Pins

• Integrated TMDS Level Translator with – 8 kV on all Auxiliary and I

C Pins

Receiver Equalization

• Enhanced Commercial Temperature Range:

• DP Port Supports Data Rates up to 2.7 Gbps

0 ° C to 85 ° C

• DP Port Supports Dual-Mode DisplayPort

• 56 Pin 8 × 8 QFN Package

• DP Port Output Waveform Mimics Input

Waveform Characteristics

• Personal Computer Market

• TMDS Port Supports Data Rates up to 2.5

– Desktop PC

Gbps

– Notebook PC

• Integrated I

C Logic Block for DVI/HDMI

– Docking Station

Connector Recognition

– Standalone Video Card

• Enhanced ESD:

The SN75DP122A is a one Dual-Mode DisplayPort input to one Dual-Mode DisplayPort output or one TMDS

output. The TMDS output has a built in level translator compliant with Digital Video Interface (DVI) 1.0 and High

Definition Multimedia Interface (HDMI) 1.3b. The DisplayPort output follows the input signal in a manner that

provides the highest level of signal integrity while supporting the EMI benefits of spread spectrum clocking.

Through the SN75DP122A data rates of up to 2.7 Gbps through each link for a total throughput of up to 10.8

Gbps can be realized. The SN75DP122A supports Display Port Spec 1.1a

In addition to the switching of the DisplayPort high speed signal lines, the SN75DP122A also supports the

switching of the bidirectional auxiliary (AUX), Hot Plug Detect (HPD), and Cable Adapter Detect (CAD) channels.

The Auxiliary differential pair supports Dual-Mode DisplayPort operation through the DisplayPort port. Through

the TMDS port the auxiliary port is configured as an I2C port with an integrated I2C repeater.

The SN75DP122A is characterized for operation over ambient air temperature of 0 ° C to 85 ° C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (37 pages)

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SN75DP122A www.ti.com............................................................................................................................................................................................ SLLS939 – NOVEMBER 2008 DisplayPort 1:2 Switch With Integrated TMDS Translator FEATURES 1 • • • • • • • • One Input Port to One of Two Output Ports Integrated TMDS Level Translator with Receiver Equalization DP Port Supports Data Rates up to 2.
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SN75DP122A SLLS939 – NOVEMBER 2008............................................................................................................................................................................................ www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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SN75DP122A LP I2C_SCL Priority TMDS_HPD_SINK I2C_EN VDD AUX(p)_I2C (SCL) AUX(n)_I2C (SDA) *1 VDD HPD CAD DP_HPD_SINK GND AUX_SINK(n) CAD_SINK www.ti.com............................................................................................................................................................................................
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SN75DP122A SLLS939 – NOVEMBER 2008............................................................................................................................................................................................ www.ti.com TERMINAL FUNCTIONS TERMINAL NAME NO.
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SN75DP122A www.ti.com............................................................................................................................................................................................ SLLS939 – NOVEMBER 2008 Table 1.
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SN75DP122A SLLS939 – NOVEMBER 2008............................................................................................................................................................................................ www.ti.com DISSIPATION RATINGS PACKAGE PCB JEDEC STANDARD TA < 25°C DERATING FACTOR (1) ABOVE TA = 25°C TA = 85°C POWER RATING Low-K 3623 mW 36.23 mW/°C 1449 mW High-K 1109 mW 11.03 mW/°C 443.
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SN75DP122A www.ti.com............................................................................................................................................................................................ SLLS939 – NOVEMBER 2008 DEVICE POWER The SN75DP122A is designed to operate off of two supply voltages. The DisplayPort port and the digital logic run off of the 5V supply voltage. The TMDS level translator is powered off of the 3.3V supply.
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SN75DP122A SLLS939 – NOVEMBER 2008............................................................................................................................................................................................ www.ti.com HPD Input HPD Output DP122A 100 kW 100 kW Figure 1. HPD Test Circuit HPD_B 0V HPD_A VDD Sink Hot Plug Detect Pulse Duration 50% 0V tPD(HPD) VDD*1 HPD Minimum Hot Plug Detect Output Pulse Duration tm(HPD) 50% 0V Figure 2.
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SN75DP122A www.ti.com............................................................................................................................................................................................ SLLS939 – NOVEMBER 2008 HPD_A & HPD_B VDD VDD Priority 50% 0V Sink Hot Plug Detect Timeout t2(HPD) t1(HPD) VDD*1 HPD 50% 0V Port B Selected Port A Selected Figure 3. HPD Timing Diagram #2 HPD_B 0V VDD HPD_A 50% 0V tZ(HPD) VDD*1 HPD 50% 0V Figure 4.
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SN75DP122A SLLS939 – NOVEMBER 2008............................................................................................................................................................................................ www.ti.com DisplayPort Auxiliary Pins The SN75DP122A is designed to support the bidirectional auxiliary signals through the DisplayPort port in both a differential (DisplayPort) mode and an I2C (DVI, HDMI) mode.
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SN75DP122A www.ti.com............................................................................................................................................................................................ SLLS939 – NOVEMBER 2008 IO = 5 mA VI = 0 V AUX+ IO = 5 mA VI = 3.6 V AUX- SN75DP122A CAD = 0 A Sink Connector Source Connector 2.5 - 3.3 V GND 100 KΩ 1 MΩ 75-200 nF 75-200 nF AUX+ 50 Ω 50 Ω 0-2 V 0-2 V 50 Ω AUX- 50 Ω 75-200 nF 75-200 nF 1 MΩ SN75DP122A 100 KΩ CAD = 0 B 3.
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SN75DP122A SLLS939 – NOVEMBER 2008............................................................................................................................................................................................ www.ti.com 2.2 V AUX Input 1.8 V Differential 0V AUX Input tPHL(AUXCO) Differential AUX Output tPLH(AUXCO) 0V Figure 8. Auxiliary Channel Delay Measurement (CAD = LOW) 3.6 V AUX Input + or - 1.8 V 0V tPHL(AUXC1) tPLH(AUXC1) 3.6 V AUX Output + or - 1.8 V 0V Figure 9.
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SN75DP122A www.ti.com............................................................................................................................................................................................
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SN75DP122A SLLS939 – NOVEMBER 2008............................................................................................................................................................................................ www.ti.com ML_IN x+ ML_IN x- Main Link 0 V Input tPD(ML) tPD(ML) Main Link Output 0V Figure 12. Main Link Delay Measurements 2.2 V ML x+ 50% 1.8 V ML xTsk1 Tsk2 2.2 V ML y+ 50% 1.8 V ML yTsk1 Figure 13.
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SN75DP122A www.ti.com............................................................................................................................................................................................ SLLS939 – NOVEMBER 2008 ELECTRICAL CHARACTERISTICS (continued) over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX Input/output capacitance AUX_I2C pins VIH(AUX) High-level input voltage AUX_I2C pins 1.
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SN75DP122A SLLS939 – NOVEMBER 2008............................................................................................................................................................................................ www.ti.com 5V VCC RL = 2 kW PULS GENERATOR D.U.T. CL = 400 pF RT VIN VOUT Figure 15. Sink Side Test Circuit (SCL, SDA) 5V I2C_SCL/ I2C_SDA Input 1.6 V 0.1 V tPHL2 tPLH2 3.3 V 80% AUX_I2C (p)/ AUX_I2C (n) Output 1.6 V 20% VOL tf1 Figure 16.
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SN75DP122A www.ti.com............................................................................................................................................................................................ SLLS939 – NOVEMBER 2008 3.3 V AUX_I2C (p)/ AUX_I2C (n) Input 0.5 V tPHL1 5V I2C_SCL/ I2C_SDA Output 1.6 V Figure 18. Sink Side Output AC Measurements Continued TMDS MAIN LINK PINS The TMDS port of the SN75DP122A is designed to be compliant with the Digital Video Interface (DVI) 1.
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SN75DP122A SLLS939 – NOVEMBER 2008............................................................................................................................................................................................ www.ti.com VTERM 3.3 V 50 W 50 W 50 W 50 W 0.5 pF D+ 100 pF VD+ Receiver VID Y Driver VY D- 100 pF Z VID = VD+ - VD- VOD = VY - VZ VICM = (VD+ + VD-) 2 VOC = (VY + VZ) 2 VD- VZ Figure 19. TMDS Main Link Test Circuit 2.2 V VTERM VID 1.
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SN75DP122A www.ti.com............................................................................................................................................................................................
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SN75DP122A SLLS939 – NOVEMBER 2008............................................................................................................................................................................................ www.ti.
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SN75DP122A www.ti.com............................................................................................................................................................................................
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SN75DP122A SLLS939 – NOVEMBER 2008............................................................................................................................................................................................ www.ti.com APPLICATION INFORMATION SWITCHING LOGIC The Switching logic of the SN75DP122A is tied to the state of the HPD pins as well as the LP and priority pins. When both HPD_A and HPD_B input pins are LOW, the SN75DP122A enters the low power state.
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SN75DP122A www.ti.com............................................................................................................................................................................................ SLLS939 – NOVEMBER 2008 • • communication link with a slave has been established. The master generates further SCL cycles to either transmit data to the slave (R/W bit 0) or receive data from the slave (R/W bit 1). In either case, the receiver needs to acknowledge the data sent by the transmitter.
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SN75DP122A SLLS939 – NOVEMBER 2008............................................................................................................................................................................................ www.ti.com address. Following this initial acknowledge by the slave, the master device becomes a receiver and acknowledges data bytes sent by the slave.
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SN75DP122A www.ti.com............................................................................................................................................................................................ SLLS939 – NOVEMBER 2008 EXAMPLE – READING FROM THE SN75DP122A The read operation consists of several steps. The I2C master begins the communication with the transmission of the start sequence followed by the slave address of the SN75DP122A.
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SN75DP122A SLLS939 – NOVEMBER 2008............................................................................................................................................................................................ www.ti.com 1 LP 0 1 Priority 0 1 HPD_A 0 1 HPD_B 0 HPD_OUT 1 Z 0 1 HI-Z Channel A 0 1 HI-Z Channel B 0 Figure 37. – Case two: In this case both HPD inputs are initially LOW and the low power pin is HIGH. In this initial state the device is in a low power mode.
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SN75DP122A www.ti.com............................................................................................................................................................................................ SLLS939 – NOVEMBER 2008 (see Figure 39). The delay of this signal through the SN75DP122A is specified as tPD(HPD). If the duration of the LOW pulse is less then tM(HPD), it may not be accurately repeated to the source.
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SN75DP122A SLLS939 – NOVEMBER 2008............................................................................................................................................................................................ www.ti.com which the previously selected port with priority goes high again is covered in scenario 3. 1 LP 0 1 Priority 0 1 HPD_A 0 1 HPD_B 0 HPD_OUT 1 Z 0 1 DATA Channel A 0 1 HI-Z Channel B 0 Figure 41.
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SN75DP122A www.ti.com............................................................................................................................................................................................ SLLS939 – NOVEMBER 2008 1 LP 0 1 Priority 0 1 HPD_A 0 1 HPD_B 0 HPD_OUT 1 Z 0 1 DATA Channel A 0 1 HI-Z Channel B 0 Figure 43. – Case two: In this case the HPD input that is initially HIGH is not the port with priority.
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SN75DP122A SLLS939 – NOVEMBER 2008............................................................................................................................................................................................ www.ti.com 1 LP 0 1 Priority 0 1 HPD_A 0 1 HPD_B 0 HPD_OUT 1 Z 0 1 DATA Channel A 0 1 HI-Z Channel B 0 Figure 45. – Case two: In this case both HPD inputs are HIGH.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN75DP122ARTQR QFN RTQ 56 2000 330.0 16.4 8.3 8.3 2.25 12.0 16.0 Q2 SN75DP122ARTQT QFN RTQ 56 250 180.0 16.4 8.3 8.3 2.25 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN75DP122ARTQR QFN RTQ 56 2000 367.0 367.0 38.0 SN75DP122ARTQT QFN RTQ 56 250 210.0 185.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.