Datasheet

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D22

D23

D24

GND

D25

D26

D27

LVDSGND

A0M

A0P

A1M

A1P

LVDSV

LVDSGND

A2M

A2P

CLKINM

CLKINP

A3M

A3P

LVDSGND

PLLGND

PLLV

PLLGND

SHTDN

CLKOUT

GND

D21

D20

D19

GND

D18

D17

D16

D15

D14

D13

GND

D12

D11

D10

GND

DGG PACKAGE

(TOP VIEW)

SN75LVDS82

www.ti.com

SLLS259I –NOVEMBER 1996– REVISED APRIL 2011

FlatLink™ RECEIVER

Check for Samples: SN75LVDS82

FEATURES

• 4:28 Data Channel Expansion at up to

238 Mbytes/s Throughput

• Suited for SVGA, XGA, or SXGA Display

Data Transmission From Controller to

Display With Very Low EMI

• Four Data Channels and Clock Low-Voltage

Differential Channels In and 28 Data and

Clock Low-Voltage TTL Channels Out

• Operates From a Single 3.3-V Supply With

250 mW (Typ)

• 5-V Tolerant SHTDN Input

• Falling Clock-Edge-Triggered Outputs

• Packaged in Thin Shrink Small-Outline

Package (TSSOP) With 20-Mil Terminal Pitch

• Consumes Less Than 1 mW When Disabled

• Wide Phase-Lock Input Frequency

Range . . . 31 MHz to 68 MHz

• No External Components Required for PLL

• Inputs Meet or Exceed the Requirements of

ANSI EIA/TIA-644 Standard

• Improved Replacement for the

National™ DS90C582

DESCRIPTION

The SN75LVDS82 FlatLink™ receiver contains four

serial-in, 7-bit parallel-out shift registers, a 7× clock

synthesizer, and five low-voltage differential signaling

(LVDS) line receivers in a single integrated circuit.

These functions allow receipt of synchronous data from a compatible transmitter, such as the SN75LVDS81,

over five balanced-pair conductors, and expansion to 28 bits of single-ended low-voltage TTL (LVTTL)

synchronous data at a lower transfer rate. The SN75LVDS82 can also be used with the SN75LVDS84 or

SN75LVDS85 for 21-bit transfers.

When receiving, the high-speed LVDS data is received and loaded into registers at the rate of seven times (7×)

the LVDS input clock (CLKIN). The data is then unloaded to a 28-bit-wide LVTTL parallel bus at the CLKIN rate.

A phase-locked loop (PLL) clock synthesizer circuit generates a 7× clock for internal clocking and an output clock

for the expanded data. The SN75LVDS82 presents valid data on the falling edge of the output clock (CLKOUT).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2FlatLink is a trademark of Texas Instruments.

3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (18 pages)

PAGE 1
SN75LVDS82 SLLS259I – NOVEMBER 1996 – REVISED APRIL 2011 www.ti.com FlatLink™ RECEIVER Check for Samples: SN75LVDS82 FEATURES 1 • 23 • • • • • • • • • • • 4:28 Data Channel Expansion at up to 238 Mbytes/s Throughput Suited for SVGA, XGA, or SXGA Display Data Transmission From Controller to Display With Very Low EMI Four Data Channels and Clock Low-Voltage Differential Channels In and 28 Data and Clock Low-Voltage TTL Channels Out Operates From a Single 3.
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SN75LVDS82 SLLS259I – NOVEMBER 1996 – REVISED APRIL 2011 www.ti.com The SN75LVDS82 requires only five line-termination resistors for the differential inputs and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user. The only possible user intervention is the use of the shutdown/clear (SHTDN) active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption.
PAGE 3
www.ti.com CLKIN ÇÇ ÇÇ ÇÇ ÇÇ ÉÉ ÉÉ ÉÉ ÉÉ Previous Cycle ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÉÉ ÉÉ ÉÉ ÉÉ Current Cycle Next Cycle D0–1 D7 D6 D4 D3 D2 D1 D0 D7+1 A1 D8–1 D18 D15 D14 D13 D12 D9 D8 D18+1 A2 D19– 1 D26 D25 D24 D22 D21 D20 D19 D26+1 D27–1 D23 D16 D11 D10 D27 D23+1 CLKOUT ÇÇÇ ÇÇÇ ÇÇÇ ÇÇÇ ÉÉÉ ÉÉÉ ÉÉÉ ÉÉÉ D17 ÇÇ ÇÇ ÇÇ ÇÇ D5 Dn – 1 D0 ÇÇ ÇÇ ÇÇ ÇÇ SLLS259I – NOVEMBER 1996 – REVISED APRIL 2011 A0 A3 SN75LVDS82 ÉÉ ÉÉ ÉÉ ÉÉ ÇÇ ÇÇ ÇÇ ÇÇ Dn Dn + 1 Figure 1.
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SN75LVDS82 SLLS259I – NOVEMBER 1996 – REVISED APRIL 2011 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) UNIT (2) –0.5 V to 4 V VCC Supply voltage range VO Output voltage range (Dxx terminals) VI Input voltage range –0.5 V to VCC + 0.5 V –0.5 V to VCC + 0.5 V Any terminal except SHTDN –0.5 V to 5.
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SN75LVDS82 SLLS259I – NOVEMBER 1996 – REVISED APRIL 2011 www.ti.com ELECTRICAL CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS TYP (1) MIN MAX UNIT 100 mV VIT+ Positive-going differential input threshold voltage VIT– Negative-going differential input threshold voltage (2) VOH High-level output voltage IOH = –4 mA VOL Low-level output voltage IOL = 4 mA 0.
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SN75LVDS82 SLLS259I – NOVEMBER 1996 – REVISED APRIL 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION AP VID VIAP AM (VIAP + VIAM)/2 VIC VIAM Figure 2. Voltage Definitions VIC – Common-Mode Input Voltage – V 2.5 Maximum at VCC >3.15 V Maximum at 3 V VCC 2 1.5 1 0.5 Minimum 0 0 0.1 0.2 0.3 0.4 0.5 0.6 |VID| – Differential Input Voltage – V Figure 3.
PAGE 7
SN75LVDS82 SLLS259I – NOVEMBER 1996 – REVISED APRIL 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) tc CLKOUT EVEN Dn ODD Dn NOTE A: The worst-case test pattern produces the maximum switching frequency for all of the outputs. Figure 5. Worst-Case Test-Pattern Waveforms tsu2 70% VOH Dn 30% VOH th2 70% VOH CLKOUT 30% VOH Figure 6.
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SN75LVDS82 SLLS259I – NOVEMBER 1996 – REVISED APRIL 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) TektronixTM HFS9003/HFS9DG1 Stimulus System (repeating patterns of F0FFFFF and 0F00000) Device Under Test (DUT) An CLKOUT CLKIN A. Tektronix Microwave Logic Multi-BERT-100RX Word Error Detector D0−D27 CLKIN is advanced or delayed with respect to data until errors are observed at the receiver outputs. The magnitude of the advance or delay is t(RSKM).
PAGE 9
SN75LVDS82 SLLS259I – NOVEMBER 1996 – REVISED APRIL 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) Reference + ∑ Device Under Test VCO + Modulation V(t) = A sin (2 π f(mod) t) HP8656B Signal Generator 0.1 MHz to 990 MHz HP8665A Synthesized Signal Generator 0.1 MHz to 990 MHz RF OUTPUT RF Output Device Under Test Digital T CLKIN CLKOUT Input Modulation Input Figure 8.
PAGE 10
SN75LVDS82 SLLS259I – NOVEMBER 1996 – REVISED APRIL 2011 www.ti.com TYPICAL CHARACTERISTICS SUPPLY CURRENT vs CLOCK FREQUENCY 85 Grayscale Data Pattern CL = 8 pF TA = 25°C 80 I CC − Supply Current − mA 75 70 VCC = 3.6 V 65 60 VCC = 3.3 V 55 50 45 40 VCC = 3 V 35 20 30 50 40 60 70 fclk − Clock Frequency − MHz Figure 11. ZERO-TO-PEAK OUTPUT JITTER vs MODULATION FREQUENCY 300 Input jitter = 750 sin (6.28 f(mod) t) ps VCC = 3.
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SN75LVDS82 SLLS259I – NOVEMBER 1996 – REVISED APRIL 2011 www.ti.
PAGE 12
SN75LVDS82 SLLS259I – NOVEMBER 1996 – REVISED APRIL 2011 Host Cable www.ti.
PAGE 13
PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 15
PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN75LVDS82DGGR Package Package Pins Type Drawing TSSOP DGG 56 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 24.4 Pack Materials-Page 1 8.6 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 15.6 1.8 12.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN75LVDS82DGGR TSSOP DGG 56 2000 367.0 367.0 45.
PAGE 17
MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
PAGE 18
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.