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SN75LVDS83A

FlatLink Transmitter

TSSOP:8x14mmDGG

Application

processor

(e.g.OMAP )

SN75LVDS83A

www.ti.com

SLLS980D –JUNE 2009– REVISED JUNE 2011

FLATLINK™ TRANSMITTER

Check for Samples: SN75LVDS83A

Low-Voltage Differential

FEATURES

• Consumes Less Than 1mW When Disabled

• LVDS Display Serdes Interfaces Directly to

• Selectable Rising or Falling Clock Edge

LCD Display Panels with Integrated LVDS

Triggered Inputs

• Package Options: 8.1mm x 14mm TSSOP

• ESD: 5kV HBM

• 3.3V Tolerant Data Inputs

• Support Spread Spectrum Clocking (SSC)

• Transfer Rate up to 100Mpps (Mega Pixel Per

• Compatible with all OMAP™2x, OMAP™3x,

Second); Pixel Clock Frequency Range 10MHz

and DaVinci™ Application Processors

to 100MHz

• Suited for Display Resolutions Ranging From

APPLICATIONS

HVGA up to HD With Low EMI

• Operates From a Single 3.3V Supply and

• LCD Display Panel Driver

170mW (typ.) at 75MHz

• UMPC and Netbook PC

• 28 Data Channels Plus Clock In Low-Voltage

• Digital Picture Frame

TTL to 4 Data Channels Plus Clock Out

DESCRIPTION

The SN75LVDS83A FlatLink™ transmitter contains four 7-bit parallel-load serial-out shift registers, a 7X clock

synthesizer, and five Low-Voltage Differential Signaling (LVDS) line drivers in a single integrated circuit. These

functions allow 28 bits of single-ended LVTTL data to be synchronously transmitted over five balanced-pair

conductors for receipt by a compatible receiver, such as the SN75LVDS82 and LCD panels with integrated LVDS

receiver.

When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock

signal (CLKIN). The rising or falling edge of the clock can be selected via the clock select (CLKSEL) pin. The

frequency of CLKIN is multiplied seven times, and then used to unload the data registers in 7-bit slices and

serially. The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers.

The frequency of CLKOUT is the same as the input clock, CLKIN.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2OMAP, DaVinci, FlatLink are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (25 pages)

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SN75LVDS83A SLLS980D – JUNE 2009 – REVISED JUNE 2011 www.ti.com FLATLINK™ TRANSMITTER Check for Samples: SN75LVDS83A FEATURES 1 • 2 • • • • • • • • LVDS Display Serdes Interfaces Directly to LCD Display Panels with Integrated LVDS Package Options: 8.1mm x 14mm TSSOP 3.3V Tolerant Data Inputs Transfer Rate up to 100Mpps (Mega Pixel Per Second); Pixel Clock Frequency Range 10MHz to 100MHz Suited for Display Resolutions Ranging From HVGA up to HD With Low EMI Operates From a Single 3.
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SN75LVDS83A SLLS980D – JUNE 2009 – REVISED JUNE 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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SN75LVDS83A SLLS980D – JUNE 2009 – REVISED JUNE 2011 www.ti.com RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN NOM MAX Supply voltage, VCC 3 3.3 3.6 LVDS output supply voltage, LVDSVCC 3 3.3 3.6 PLL analog supply voltage, PLLVCC 3 3.3 3.6 Power supply noise on any VCC terminal UNIT V 0.1 High-level input voltage, VIH VCC/2 + 0.
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SN75LVDS83A SLLS980D – JUNE 2009 – REVISED JUNE 2011 www.ti.
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SN75LVDS83A SLLS980D – JUNE 2009 – REVISED JUNE 2011 www.ti.com PIN FUNCTIONS TERMINAL I/O Y0P, Y0M, Y1P, Y1M, Y2P, Y2M Y3P, Y3M DESCRIPTION Differential LVDS data outputs. Outputs are high-impedance when SHTDN is pulled low (de-asserted) LVDS Out Differential LVDS Data outputs. Output is high-impedance when SHTDN is pulled low (de-asserted). Note: if the application only requires 18-bit color, this output can be left open. CLKP, CLKM Differential LVDS pixel clock output.
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SN75LVDS83A SLLS980D – JUNE 2009 – REVISED JUNE 2011 www.ti.com FUNCTIONAL BLOCK DIAGRAM Parallel-Load 7-bit Shift Register D0, D1, D2, D3, D4, D6, D7 7 Y0P A,B,...G SHIFT/LOAD >CLK Y0M Parallel-Load 7-bit Shift Register D8, D9, D12, D13, D14, D15, D18 7 Y1P A,B,...G SHIFT/LOAD >CLK Y1M Parallel-Load 7-bit Shift Register D19, D20, D21, D22, D24, D25, D26 7 Y2P A,B,...G SHIFT/LOAD >CLK Y2M Parallel-Load 7-bit Shift Register D27, D5, D10, D11, D16, D17, D23 7 Y3P Y3M A,B,...
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SN75LVDS83A SLLS980D – JUNE 2009 – REVISED JUNE 2011 www.ti.com Dn CLKIN or CLKIN CLKOUT Previous cycle Next Current cycle Y0 D0-1 D7 D6 D4 D3 D2 D1 D0 D7+1 Y1 D8-1 D18 D15 D14 D13 D12 D9 D8 D18+1 Y2 D19-1 D26 D25 D24 D22 D21 D20 D19 D26+1 Y3 D27-1 D23 D17 D16 D11 D10 D5 D27 D23+1 Figure 1. Typical SN75LVDS83A Load and Shift Sequences LVDSVCC VCC 5W D or SHTDN 50W 7V YnP or YnM 10kW 300kW 7V Figure 2.
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SN75LVDS83A SLLS980D – JUNE 2009 – REVISED JUNE 2011 www.ti.
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SN75LVDS83A SLLS980D – JUNE 2009 – REVISED JUNE 2011 www.ti.com SWITCHING CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX -0.1 0 0.1 ns UNIT t0 Delay time, CLKOUT↑ after Yn valid (serial bit position 0, equal D1, D9, D20, D5) t1 Delay time, CLKOUT↑ after Yn valid (serial bit position 1, equal D0, D8, D19, D27) 1 /7 tc - 0.1 1 /7 tc + 0.
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SN75LVDS83A SLLS980D – JUNE 2009 – REVISED JUNE 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION tsu thold Dn CLKIN All input timing is defined at IOVDD / 2 on an input signal with a 10% to 90% rise or fall time of less than 3 ns. CLKSEL = 0V. Figure 3. Set Up and Hold Time Definition 49.9W ± 1% (2 PLCS) YP VOD VOC YM 100% 80% VOD(H) 0V VOD(L) 20% 0% tf tr VOC(PP) VOC(SS) VOC(SS) 0V Figure 4. Test Load and Voltage Definitions for LVDS Outputs.
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SN75LVDS83A SLLS980D – JUNE 2009 – REVISED JUNE 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) T CLKIN EVEN Dn ODD Dn The worst-case test pattern produces nearly the maximum switching frequency for all of the LVDS outputs. Figure 6. Worst-Case Power Test Pattern t7 CLKIN CLKOUT t6 t5 t4 t3 t2 t1 t0 Yn ~2.5V 1.40V CLKIN VOD(H) CLKOUT or Yn 0.00V ~0.5V t7 VOD(L) t0-6 CLKOUT is shown with CLKSEL at high-level. CLKIN polarity depends on CLKSEL input level. Figure 7.
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SN75LVDS83A SLLS980D – JUNE 2009 – REVISED JUNE 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) Reference + Device Under Test VCO + Modulation v(t) = A sin(2 pfmodt) HP8656B Signal Generator, 0.1 MHz-990 MHz RF Output HP8665A Synthesized Signal Generator, 0.1 MHz-4200 MHz Device Under Test RF Output Modulation Input CLKIN CLKOUT DTS2070C Digital TimeScope Input Figure 8. Output Clock Jitter Test Set Up CLKIN Dn ten SHTDN Invalid Yn Valid Figure 9.
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SN75LVDS83A SLLS980D – JUNE 2009 – REVISED JUNE 2011 www.ti.com TYPICAL CHARACTERISTICS AVERAGE GRAYSCALE ICC vs CLOCK FREQUENCY 800 Total Device Current (Using Grayscale pattern) Over Pixel Clock Frequency Output Jitter 90 700 80 600 Period Clock Jitter - ps-pp ICC - Average Supply Current - mA 100 OUTPUT CLOCK JITTER vs INPUT CLOCK JITTER 70 VCC = 3.6V 60 50 VCC = 3.
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SN75LVDS83A SLLS980D – JUNE 2009 – REVISED JUNE 2011 www.ti.com APPLICATION INFORMATION This section describes the power up sequence, provides information on device connectivity to various GPU and LCD display panels, and offers a pcb routing example. Power Up Sequence The SN75LVDS83A does not require a specific power up sequence. The user experience can be impacted by the way a system powers up and powers down an LCD screen.
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SN75LVDS83A SLLS980D – JUNE 2009 – REVISED JUNE 2011 www.ti.com 4.8k 3.
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SN75LVDS83A SLLS980D – JUNE 2009 – REVISED JUNE 2011 www.ti.com SN75LVDS83A to column driver LVDS timing 100 Controller (6-bpc, 18-bpp) Panel connector FPC Cable 100 to row driver 18-bpp LCD Display Y3M Y3P (See Note A) 4.8k 3.
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SN75LVDS83A SLLS980D – JUNE 2009 – REVISED JUNE 2011 www.ti.com 12-bpp GPU SN75LVDS83A (See Note B) B2or VCC B3 or GND B0 B1 B2 B3(MSB) Y1M Y1P 100 FPC Cable LVDS timing 100 Controller (6-bpc, 18-bpp) Panel connector Main board connector to column driver CLKOUTM CLKOUTP 100 to row driver 18-bpp LCD Display Y3M Y3P (See Note A) VCC GND HSYNC VSYNC ENABLE RSVD CLK 100 4.8k 3.
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SN75LVDS83A SLLS980D – JUNE 2009 – REVISED JUNE 2011 www.ti.com 24-bpp GPU SN75LVDS83A R0 and R1: N.C. G7(MSB) (See Note B) B0 and B1: N.C. (See Note B) B2 B3 B4 B5 B6 100 to column driver LVDS timing 100 Controller (6-bpc, 18-bpp) Panel connector FPC Cable CLKOUTM CLKOUTP 100 to row driver 18-bpp LCD Display Y3M Y3P (See Note A) 4.8k 3.3V Y1M Y1P Y2M Y2P VCC GND B7(MSB) B0 -> N.C. B1 -> N.C.
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SN75LVDS83A SLLS980D – JUNE 2009 – REVISED JUNE 2011 www.ti.com Typical Application Schematic Figure 18 represents the schematic drawing of the SN75LVDS83A evaluation module. J1 U1H GND1 GND2 GND3 GND4 GND5 GND6 GND7 PLLGND LVDSGND1 LVDSGND2 J3 CLKM CLKP Y0P Y0M Y1P Y1M Y2P Y2M VCC R4 4.7k R5 4.7k R6 4.7k R7 4.7k R8 4.7k R9 4.7k Y3P Y3M R10 4.
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SN75LVDS83A SLLS980D – JUNE 2009 – REVISED JUNE 2011 www.ti.com REVISION HISTORY Changes from Original (June 2009) to Revision A Page • Changed Description text From: Alternative device option: The SN75LVDS83A is an alternative... To: Alternative device option: The SN75LVDS83B is an alternative... ......................................................................................................... 2 • Changed Figure 13 - TYPICAL PRBS OUTPUT SIGNAL OVER ONE CLOCK PERIOD ...........................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN75LVDS83ADGGR Package Package Pins Type Drawing TSSOP DGG 56 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 24.4 Pack Materials-Page 1 8.6 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 15.6 1.8 12.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN75LVDS83ADGGR TSSOP DGG 56 2000 367.0 367.0 45.
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MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
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