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SN75LVDS83B

FlatLink Transmitter

PackageOptions

TSSOP:8x14mmDGG

BGA:4.5x7mm

Application

processor

(e.g.OMAP )

SN75LVDS83B

www.ti.com

SLLS846B –MAY 2009–REVISED SEPTEMBER 2011

FLATLINK™ TRANSMITTER

Check for Samples: SN75LVDS83B

FEATURES

Voltage Differential

• Consumes Less Than 1mW When Disabled

• LVDS Display Serdes Interfaces Directly to

LCD Display Panels with Integrated LVDS

• Selectable Rising or Falling Clock Edge

Triggered Inputs

• Package Options: 4.5mm x 7mm BGA, and

8.1mm x 14mm TSSOP

• ESD: 5kV HBM

• 1.8V up to 3.3V Tolerant Data Inputs to

• Support Spread Spectrum Clocking (SSC)

Connect Directly to Low-Power, Low-Voltage

• Compatible with all OMAP™2x, OMAP™3x,

Application and Graphic Processors

and DaVinci™ Application Processors

• Transfer Rate up to 135Mpps (Mega Pixel Per

Second); Pixel Clock Frequency Range 10MHz

APPLICATIONS

to 135MHz

• LCD Display Panel Driver

• Suited for Display Resolutions Ranging From

• UMPC and Netbook PC

HVGA up to HD With Low EMI

• Digital Picture Frame

• Operates From a Single 3.3V Supply and

170mW (typ.) at 75MHz

• 28 Data Channels Plus Clock In Low-Voltage

TTL to 4 Data Channels Plus Clock Out Low-

DESCRIPTION

The SN75LVDS83B FlatLink™ transmitter contains four 7-bit parallel-load serial-out shift registers, a 7X clock

synthesizer, and five Low-Voltage Differential Signaling (LVDS) line drivers in a single integrated circuit. These

functions allow 28 bits of single-ended LVTTL data to be synchronously transmitted over five balanced-pair

conductors for receipt by a compatible receiver, such as the SN75LVDS82 and LCD panels with integrated LVDS

receiver.

When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock

signal (CLKIN). The rising or falling edge of the clock can be selected via the clock select (CLKSEL) pin. The

frequency of CLKIN is multiplied seven times, and then used to unload the data registers in 7-bit slices and

serially. The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers.

The frequency of CLKOUT is the same as the input clock, CLKIN.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2OMAP, DaVinci, FlatLink are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (30 pages)

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SN75LVDS83B www.ti.com SLLS846B – MAY 2009 – REVISED SEPTEMBER 2011 FLATLINK™ TRANSMITTER Check for Samples: SN75LVDS83B FEATURES 1 • 2 • • • • • • • • LVDS Display Serdes Interfaces Directly to LCD Display Panels with Integrated LVDS Package Options: 4.5mm x 7mm BGA, and 8.1mm x 14mm TSSOP 1.8V up to 3.
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SN75LVDS83B SLLS846B – MAY 2009 – REVISED SEPTEMBER 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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SN75LVDS83B www.ti.com SLLS846B – MAY 2009 – REVISED SEPTEMBER 2011 RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) PARAMETER MIN NOM MAX Supply voltage, VCC 3 3.3 3.6 LVDS output Supply voltage, LVDSVCC 3 3.3 3.6 PLL analog supply voltage, PLLVCC 3 3.3 3.6 1.62 1.8 / 2.5 / 3.3 3.6 IO input reference supply voltage, IOVCC Power supply noise on any VCC terminal UNIT V 0.
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SN75LVDS83B SLLS846B – MAY 2009 – REVISED SEPTEMBER 2011 www.ti.
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SN75LVDS83B www.ti.
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SN75LVDS83B SLLS846B – MAY 2009 – REVISED SEPTEMBER 2011 www.ti.com ZQL PIN LIST (continued) K1 D1 K2 D2 K3 D4 K4 D5 K5 D7 K6 D8 PIN FUNCTIONS TERMINAL I/O Y0P, Y0M, Y1P, Y1M, Y2P, Y2M Y3P, Y3M DESCRIPTION Differential LVDS data outputs. Outputs are high-impedance when SHTDN is pulled low (de-asserted) LVDS Out Differential LVDS Data outputs. Output is high-impedance when SHTDN is pulled low (de-asserted). Note: if the application only requires 18-bit color, this output can be left open.
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SN75LVDS83B www.ti.com SLLS846B – MAY 2009 – REVISED SEPTEMBER 2011 FUNCTIONAL BLOCK DIAGRAM Parallel-Load 7-bit Shift Register D0, D1, D2, D3, D4, D6, D7 7 A,B,...G SHIFT/LOAD >CLK Y0P Y0M Parallel-Load 7-bit Shift Register D8, D9, D12, D13, D14, D15, D18 7 A,B,...G SHIFT/LOAD >CLK Y1P Y1M Parallel-Load 7-bit Shift Register D19, D20, D21, D22, D24, D25, D26 7 A,B,...G SHIFT/LOAD >CLK Y2P Y2M Parallel-Load 7-bit Shift Register D27, D5, D10, D11, D16, D17, D23 7 A,B,...
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SN75LVDS83B SLLS846B – MAY 2009 – REVISED SEPTEMBER 2011 www.ti.com Dn CLKIN or CLKIN CLKOUT Previous cycle Next Current cycle Y0 D0-1 D7 D6 D4 D3 D2 D1 D0 D7+1 Y1 D8-1 D18 D15 D14 D13 D12 D9 D8 D18+1 Y2 D19-1 D26 D25 D24 D22 D21 D20 D19 D26+1 Y3 D27-1 D23 D17 D16 D11 D10 D5 D27 D23+1 Figure 1. Typical SN75LVDS83B Load and Shift Sequences LVDSVCC IOVCC 5W D or SHTDN 50W 7V YnP or YnM 10kW 300kW 7V Figure 2.
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SN75LVDS83B www.ti.
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SN75LVDS83B SLLS846B – MAY 2009 – REVISED SEPTEMBER 2011 www.ti.com SWITCHING CHARACTERISTICS over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP (1) MAX -0.1 0 0.1 ns UNIT t0 Delay time, CLKOUT↑ after Yn valid (serial bit position 0, equal D1, D9, D20, D5) t1 Delay time, CLKOUT↑ after Yn valid (serial bit position 1, equal D0, D8, D19, D27) 1 /7 tc - 0.1 1 /7 tc + 0.
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SN75LVDS83B www.ti.com SLLS846B – MAY 2009 – REVISED SEPTEMBER 2011 THERMAL CHARACTERISTICS (continued) PARAMETER ZQL TEST CONDITIONS ψJB Junction-to-board MIN EIA/JESD 51-6 TA Operating ambient temperature range TJ Virtual junction temperature TYP DGG MAX MIN 30.3 TYP MAX 32.
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SN75LVDS83B SLLS846B – MAY 2009 – REVISED SEPTEMBER 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) CLKIN D0,8,16 D1,9,17 D2,10,18 D3,11,19 D4-7,12-15,20-23 D24-27 The 16 grayscale test pattern test device power consumption for a typical display pattern. Figure 5. 16 Grayscale Test Pattern T CLKIN EVEN Dn ODD Dn The worst-case test pattern produces nearly the maximum switching frequency for all of the LVDS outputs. Figure 6.
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SN75LVDS83B www.ti.com SLLS846B – MAY 2009 – REVISED SEPTEMBER 2011 PARAMETER MEASUREMENT INFORMATION (continued) + Reference Device Under Test VCO + Modulation v(t) = A sin(2 pfmodt) HP8656B Signal Generator, 0.1 MHz-990 MHz RF Output HP8665A Synthesized Signal Generator, 0.1 MHz-4200 MHz Device Under Test RF Output Modulation Input CLKIN CLKOUT DTS2070C Digital TimeScope Input Figure 8. Output Clock Jitter Test Set Up CLKIN Dn ten SHTDN Invalid Yn Valid Figure 9.
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SN75LVDS83B SLLS846B – MAY 2009 – REVISED SEPTEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS AVERAGE GRAYSCALE ICC vs CLOCK FREQUENCY 100 OUTPUT CLOCK JITTER vs INPUT CLOCK JITTER 800 Total Device Current (Using Grayscale pattern) Over Pixel Clock Frequency Output Jitter 700 80 Period Clock Jitter - ps-pp ICC - Average Supply Current - mA 90 VCC = 3.6V 70 60 50 VCC = 3.
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SN75LVDS83B www.ti.com SLLS846B – MAY 2009 – REVISED SEPTEMBER 2011 APPLICATION INFORMATION This section describes the power up sequence, provides information on device connectivity to various GPU and LCD display panels, and offers a pcb routing example. Power Up Sequence The SN75LVDS83B does not require a specific power up sequence. It is permitted to power up IOVCC while VCC, VCCPLL, and VCCLVDS remain powered down and connected to GND.
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SN75LVDS83B SLLS846B – MAY 2009 – REVISED SEPTEMBER 2011 www.ti.com SN75LVDS83B 4.8k 1.8V or 2.5V or 3.
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SN75LVDS83B www.ti.com SLLS846B – MAY 2009 – REVISED SEPTEMBER 2011 SN75LVDS83B B0(LSB) B1 B2 B3 B4 B5(MSB) C1 100 FPC Cable Panel connector to column driver CLKOUTM CLKOUTP LVDS timing Controller (6-bpc, 18-bpp) 100 100 to row driver 18-bpp LCD Display Y3M Y3P 4.8k 1.8V or 2.5V or 3.
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SN75LVDS83B SLLS846B – MAY 2009 – REVISED SEPTEMBER 2011 12-bpp GPU www.ti.com SN75LVDS83B (See Note B) D0 D1 D2 D3 D4 D6 D27 D5 D7 D8 D9 D12 D13 D14 D10 D11 D15 D18 D19 D20 D21 D22 D16 D17 D24 D25 D26 D23 CLKIN (See Note B) B2 or VCC B3 or GND B0 B1 B2 B3(MSB) C1 FPC Cable t Panell connector Main board connector CLKOUTM CLKOUTP LVDS timing Controller (6-bpc, 18-bpp) 100 100 to row driver 18-bpp LCD Display Y3M Y3P 4.8k 1.8V or 2.5V or 3.
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SN75LVDS83B www.ti.com SLLS846B – MAY 2009 – REVISED SEPTEMBER 2011 SN75LVDS83B D0 D1 D2 D3 D4 D6 D27 D5 D7 D8 D9 D12 D13 D14 D10 D11 D15 D18 D19 D20 D21 D22 D16 D17 D24 D25 D26 D23 CLKIN G7(MSB) B0 and B1: NC (See Note B) B2 B3 B4 B5 B6 B7(MSB) B0 and B1: NC (See Note B) CLKOUTM CLKOUTP C1 FPC Cable LVDS timing Controller (6-bpc, 18-bpp) 100 100 to row driver 18-bpp LCD Display Y3M Y3P 4.8k 1.8V or 2.5V or 3.
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SN75LVDS83B SLLS846B – MAY 2009 – REVISED SEPTEMBER 2011 www.ti.com Typical Application Schematic Figure 18 represents the schematic drawing of the SN75LVDS83B evaluation module. J1 U1H GND1 GND2 GND3 GND4 GND5 GND6 GND7 PLLGND LVDSGND1 LVDSGND2 J3 CLKM CLKP Y0P Y0M Y1P Y1M Y2P Y2M IOVCC R4 4.7k R5 4.7k R6 4.7k R7 4.7k R8 4.7k R9 4.7k Y3P Y3M R10 4.
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SN75LVDS83B www.ti.com SLLS846B – MAY 2009 – REVISED SEPTEMBER 2011 PCB Routing Figure 19 and Figure 20 show a possible breakout of the data input and output signals from the BGA package.
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SN75LVDS83B SLLS846B – MAY 2009 – REVISED SEPTEMBER 2011 www.ti.com G1 G0 D8 D7 R5 R4 R3 R2 D5 D4 D2 R1 R0 D1 To GND G2 G3 D9 GND D6 D3 D0 D27 D11 VCC D10 GND Y0P Y0M D13 D12 IOVCC GND Y1P Y1M D14 GND D16 D15 D17 D18 CLKSEL D19 GND IOVCC G4 G5 B0 LVDS GND LVDS VCC To GND B1 Y2P Y2M GND CLKP CLKM GND Y3P Y3M B2 remains unconnected B3 B4 D20 D21 D22 D23 D25 SHTDN PLLVCC LVDS GND +PLL GND CLKIN B5 D24 PLL GND D26 HS VS EN CLK Figure 20.
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SN75LVDS83B www.ti.com SLLS846B – MAY 2009 – REVISED SEPTEMBER 2011 REVISION HISTORY Changes from Original (May 2009) to Revision A Page • Changed text and replaced TBDs in Note A and Note B of Figure 14 ............................................................................... 16 • Changed Note B of Figure 15 - Replaced TBDs. ............................................................................................................... 17 • Changed Note B of Figure 16 - Replaced TBDs. .......
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 21-Apr-2013 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN75LVDS83BZQLR Package Package Pins Type Drawing BGA MI CROSTA R JUNI OR ZQL 56 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 16.4 Pack Materials-Page 1 4.8 B0 (mm) K0 (mm) P1 (mm) 7.3 1.5 8.0 W Pin1 (mm) Quadrant 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN75LVDS83BZQLR BGA MICROSTAR JUNIOR ZQL 56 1000 336.6 336.6 28.
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MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.