Datasheet

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 

SLLS271I − MARCH 1997 − REVISED MAY 2009

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D 4:28 Data Channel Compression at up to

238 MBytes/s Throughput

D Suited for SVGA, XGA, or SXGA Display

Data Transmission From Controller to

Display With Very Low EMI

D 28 Data Channels and Clock-In Low-Voltage

TTL

D 4 Data Channels and Clock-Out

Low-Voltage Differential

D Operates From a Single 3.3-V Supply With

250 mW (Typ)

D ESD Protection Exceeds 6 kV

D 5-V Tolerant Data Inputs

D Selectable Rising or Falling Edge-Triggered

Inputs

D Packaged in Thin Shrink Small-Outline

Package With 20-Mil Terminal Pitch

D Consumes Less Than 1 mW When Disabled

D Wide Phase-Lock Input Frequency

Range . . . 31 MHz to 68 MHz

D No External Components Required for PLL

D Outputs Meet or Exceed the Requirements

of ANSI EIA/TIA-644 Standard

D Improved Replacement for the DS90C581

description

The SN75LVDS83 FlatLink transmitter contains

four 7-bit parallel-load serial-out shift registers, a

7× clock synthesizer, and five low-voltage

differential-signaling (LVDS) line drivers in a single integrated circuit. These functions allow 28 bits of

single-ended low-voltage TTL (LVTTL) data to be synchronously transmitted over five balanced-pair conductors

for receipt by a compatible receiver, such as the SN75LVDS82. The SN75LVDS83 can also be used in 21-bit

links with the SN75LVDS86 receiver.

When transmitting, data bits D0 through D27 are each loaded into registers upon the edge of the input clock

signal (CLKIN). The rising or falling edge of the clock can be selected by way of the clock select (CLKSEL)

terminal. The frequency of CLKIN is multiplied seven times (7×) and then used to unload the data registers in

7-bit slices and serially. The four serial streams and a phase-locked clock (CLKOUT) are then output to LVDS

output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.

The SN75LVDS83 requires no external components and little or no control. The data bus appears the same

at the input to the transmitter and output of the receiver with the data transmission transparent to the user. The

only user intervention is the possible use of the shutdown/clear (SHTDN

) active-low input to inhibit the clock

and shut off the LVDS output drivers for lower power consumption. A low-level signal on SHTDN

clears all

internal registers to a low level.

The SN75LVDS83 is characterized for operation over free-air temperature ranges of 0_C to 70_C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

GND

D10

D11

D12

D13

GND

D14

D15

D16

CLKSEL

D17

D18

D19

GND

D20

D21

D22

D23

D24

D25

GND

D27

LVDSGND

Y0M

Y0P

Y1M

Y1P

LVDSV

LVDSGND

Y2M

Y2P

CLKOUTM

CLKOUTP

Y3M

Y3P

LVDSGND

PLLGND

PLLV

PLLGND

SHTDN

CLKIN

D26

GND

DGG PACKAGE

(TOP VIEW)

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FlatLink is a registered trademark of Texas Instruments.

Not Recommended for New Designs

Summary of content (21 pages)

PAGE 1
Not Recommended for New Designs  SLLS271I − MARCH 1997 − REVISED MAY 2009 D 4:28 Data Channel Compression at up to D D D D D D D D D D D D D 238 MBytes/s Throughput Suited for SVGA, XGA, or SXGA Display Data Transmission From Controller to Display With Very Low EMI 28 Data Channels and Clock-In Low-Voltage TTL 4 Data Channels and Clock-Out Low-Voltage Differential Operates From a Single 3.
PAGE 2
Not Recommended for New Designs  SLLS271I − MARCH 1997 − REVISED MAY 2009 functional block diagram D0, D1, D2, D3, D4, D6, D7 Parallel-Load 7-Bit Shift Register 7 A,B, ...G SHIFT/LOAD Y0P Y0M CLK D8, D9, D12, D13, D14, D15, D18 Parallel-Load 7-Bit Shift Register 7 Y1P A,B, ...G SHIFT/LOAD Y1M CLK D27, D5, D10, D11, D16, D17, D23 Y2P A,B, ...
PAGE 3
Not Recommended for New Designs D0 ÉÉÉ ÉÉÉ  SLLS271I − MARCH 1997 − REVISED MAY 2009 ÉÉÉ ÉÉÉ CLKIN or CLKIN ÉÉ ÉÉ CLKOUT ÇÇ ÇÇ ÉÉ ÉÉ Previous Cycle ÇÇ ÇÇ Next Cycle Current Cycle Y0 D0−1 D7 D6 D4 D3 D2 D1 D0 D7+1 Y1 D8−1 D18 D15 D14 D13 D12 D9 D8 D18+1 Y2 D19−1 D26 D25 D24 D22 D21 D20 D19 D26+1 Y3 D27−1 D23 D17 D16 D11 D10 D5 D27 D23+1 Figure 1.
PAGE 4
 Not Recommended for New Designs SLLS271I − MARCH 1997 − REVISED MAY 2009 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4 V Output voltage range, VO (all terminals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.
PAGE 5
Not Recommended for New Designs  SLLS271I − MARCH 1997 − REVISED MAY 2009 electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS VIT |VOD| Input threshold voltage ∆|VOD| Change in the steady-state differential output voltage magnitude between opposite binary states VOC(SS) VOC(PP) Steady-state common-mode output voltage IIH IIL High-level input current TYP† MAX UNIT 454 mV 50 mV 1.
PAGE 6
 Not Recommended for New Designs SLLS271I − MARCH 1997 − REVISED MAY 2009 switching characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† 0 td0 Delay time, CLKOUT↑ to serial bit position 0 −0.2 td1 Delay time, CLKOUT↑ to serial bit position 1 td2 Delay time, CLKOUT↑ to serial bit position 2 td3 td4 Delay time, CLKOUT↑ to serial bit position 3 tc = 15.38 ns (± 0.
PAGE 7
Not Recommended for New Designs  SLLS271I − MARCH 1997 − REVISED MAY 2009 PARAMETER MEASUREMENT INFORMATION ÉÉÉÉÉ ÉÉÉÉÉ Dn tsu th ÉÉÉÉ ÉÉÉÉ CLKSEL LOW CLKIN CLKSEL HIGH NOTE A: All input timing is defined at 1.4 V on an input signal with a 10%-to-90% rise or fall time of less than 5 ns. Figure 2. Setup and Hold Time Waveforms 49.
PAGE 8
Not Recommended for New Designs  SLLS271I − MARCH 1997 − REVISED MAY 2009 PARAMETER MEASUREMENT INFORMATION CLKIN D0, 8, 16 D1, 9, 17 D2, 10, 18 D3, 11, 19 D4−7, 12−15, 20−23 D24−27 NOTE A: The 16-grayscale test-pattern test device power consumption for a typical display pattern. Pattern with CLKSEL low shown. Figure 4.
PAGE 9
Not Recommended for New Designs  SLLS271I − MARCH 1997 − REVISED MAY 2009 PARAMETER MEASUREMENT INFORMATION td7 CLKIN (see Note A) CLKIN (see Note B) CLKOUT Yn ÏÏÏ ÏÏÏ ÏÏÏ ÉÉ ÉÉ td1 ÎÎ ÎÎ ÎÎ td0 ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÉÉ ÏÏ ÏÏ ÏÏ ÉÉ ÉÉ ÉÉÉ ÉÉ ÉÉ ÉÉ ÉÉÉ ÉÉ td2 td3 td4 td5 td6 ≈ 2.5 V CLKIN 1.4 V VOD(H) CLKOUT or Yn 0.00 V ≈ 0.5 V VOD(L) td7 td0 − td6 NOTES: A. This wave form is valid when CLKSEL is low. B. This wave form is valid when CLKSEL is high. Figure 6.
PAGE 10
Not Recommended for New Designs  SLLS271I − MARCH 1997 − REVISED MAY 2009 PARAMETER MEASUREMENT INFORMATION Reference + ∑ Device Under Test VCO + Modulation V(t) = A sin (2 π f(mod) t) HP8656B Signal Generator 0.1 MHz − 990 MHz HP8665A Synthesized Signal Generator 0.1 MHz − 4200 MHz Device Under Test OUTPUT RF Output CLKIN CLKOUT DTS2070C Digital Time Scope Input Modulation Input Figure 7.
PAGE 11
Not Recommended for New Designs  SLLS271I − MARCH 1997 − REVISED MAY 2009 TYPICAL CHARACTERISTICS AVERAGE SUPPLY CURRENT vs CLOCK FREQUENCY I CC − Average Supply Current − mA 80 VCC = 3.6 V 70 60 VCC = 3.3 V 50 VCC = 3 V 40 Grayscale Data Pattern RL = 100 Ω TA = 25°C 30 30 40 50 60 70 fclk − Clock Frequency − MHz Figure 10 ZERO-TO-PEAK OUTPUT JITTER vs MODULATION FREQUENCY 200 Zero-to-Peak Output Jitter − ps 180 160 140 120 100 80 60 40 Input jitter = 750 sin (6.
PAGE 12
Not Recommended for New Designs  SLLS271I − MARCH 1997 − REVISED MAY 2009 APPLICATION INFORMATION Host Graphic Controller 12-BIT RED0 RED1 RED2 RED3 RSVD RSVD NA NA GREEN0 GREEN1 GREEN2 GREEN3 RSVD RSVD NA NA BLUE0 BLUE1 BLUE2 BLUE3 RSVD RSVD NA NA H_SYNC V_SYNC ENABLE NA CLOCK 18-BIT RED0 RED1 RED2 RED3 RED4 RED5 NA NA GREEN0 GREEN1 GREEN2 GREEN3 GREEN4 GREEN5 NA NA BLUE0 BLUE1 BLUE2 BLUE3 BLUE4 BLUE5 NA NA H_SYNC V_SYNC ENABLE NA CLOCK Cable Flat Panel Display SN75LVDS83
PAGE 13
Not Recommended for New Designs  SLLS271I − MARCH 1997 − REVISED MAY 2009 APPLICATION INFORMATION Host Graphic Controller 12-BIT RED0 RED1 RED2 RED3 RSVD RSVD NA NA GREEN0 GREEN1 GREEN2 GREEN3 RSVD RSVD NA NA BLUE0 BLUE1 BLUE2 BLUE3 RSVD RSVD NA NA H_SYNC V_SYNC ENABLE NA CLOCK 18-BIT RED0 RED1 RED2 RED3 RED4 RED5 NA NA GREEN0 GREEN1 GREEN2 GREEN3 GREEN4 GREEN5 NA NA BLUE0 BLUE1 BLUE2 BLUE3 BLUE4 BLUE5 NA NA H_SYNC V_SYNC ENABLE NA CLOCK Cable Flat Panel Display SN75LVDS83
PAGE 14
PACKAGE OPTION ADDENDUM www.ti.
PAGE 15
PACKAGE OPTION ADDENDUM www.ti.com 1-May-2013 (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
PAGE 16
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN75LVDS83DGGR Package Package Pins Type Drawing TSSOP DGG 56 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 24.4 Pack Materials-Page 1 8.6 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 15.6 1.8 12.0 24.
PAGE 17
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN75LVDS83DGGR TSSOP DGG 56 2000 367.0 367.0 45.
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MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
PAGE 21
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.