Datasheet

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SN75LVDS84A, SN65LVDS84AQ

FLATLINK TRANSMITTER

SLLS354E – MAY 1999 – REVISED JANUARY 2001

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

21:3 Data Channel Compression at up to

196 Million Bytes per Second Throughput

Suited for SVGA, XGA, or SXGA Data

Transmission From Controller to Display

With Very Low EMI

21 Data Channels Plus Clock In

Low-Voltage TTL Inputs and 3 Data

Channels Plus Clock Out Low-Voltage

Differential Signaling (LVDS) Outputs

Operates From a Single 3.3-V Supply and

89 mW (Typ)

Ultralow-Power 3.3-V CMOS Version of the

SN75LVDS84. Power Consumption About

One Third of the ’LVDS84

Packaged in Thin Shrink Small-Outline

Package (TSSOP) With 20 Mil Terminal

Pitch

Consumes Less Than 0.54 mW When

Disabled

Wide Phase-Lock Input Frequency Range:

31 MHz to 75 MHz

No External Components Required for PLL

Outputs Meet or Exceed the Requirements

of ANSI EIA/TIA-644 Standard

SSC Tracking Capability of 3% Center

Spread at 50-kHz Modulation Frequency

Improved Replacement for SN75LVDS84

and NSC’s DS90CF363A 3-V Device

Available in Q-Temp Automotive

High Reliability Automotive Applications

Configuration Control / Print Support

Qualification to Automotive Standards

description

The SN75LVDS84A and SN65LVDS84AQ FlatLink transmitters contains three 7-bit parallel-load serial-out shift

registers, and four low-voltage differential signaling (LVDS) line drivers in a single integrated circuit. These

functions allow 21 bits of single-ended LVTTL data to be synchronously transmitted over 3 balanced-pair

conductors for receipt by a compatible receiver, such as the SN75LVDS82 or SN75LVDS86/86A.

When transmitting, data bits D0 – D20 are each loaded into registers of the ’LVDS84A upon the falling edge.

The internal PLL is frequency-locked to CLKIN and then used to unload the data registers in 7-bit slices. The

three serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency

of CLKOUT is the same as the input clock, CLKIN.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

FlatLink is a trademark of Texas Instruments.

GND

D10

GND

D11

D12

D13

D14

GND

D15

D16

D17

D18

D19

GND

LVDSGND

Y0M

Y0P

Y1M

Y1P

LVDSV

LVDSGND

Y2M

Y2P

CLKOUTM

CLKOUTP

LVDSGND

PLLGND

PLLV

PLLGND

SHTDN

CLKIN

D20

DGG PACKAGE

(TOP VIEW)

NC – Not Connected

Summary of content (17 pages)

PAGE 1
SN75LVDS84A, SN65LVDS84AQ FLATLINK TRANSMITTER SLLS354E – MAY 1999 – REVISED JANUARY 2001 D D D D D D D D D D D D D 21:3 Data Channel Compression at up to 196 Million Bytes per Second Throughput Suited for SVGA, XGA, or SXGA Data Transmission From Controller to Display With Very Low EMI 21 Data Channels Plus Clock In Low-Voltage TTL Inputs and 3 Data Channels Plus Clock Out Low-Voltage Differential Signaling (LVDS) Outputs Operates From a Single 3.3-V Supply and 89 mW (Typ) Ultralow-Power 3.
PAGE 2
SN75LVDS84A, SN65LVDS84AQ FLATLINK TRANSMITTER SLLS354E – MAY 1999 – REVISED JANUARY 2001 description (continued) The ’LVDS84A requires no external components and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only user intervention is the possible use of the shutdown/clear (SHTDN) active-low input to inhibit the clock and shut off the LVDS output drivers for lower power consumption.
PAGE 3
SN75LVDS84A, SN65LVDS84AQ FLATLINK TRANSMITTER SLLS354E – MAY 1999 – REVISED JANUARY 2001 schematics of input and output EQUIVALENT OF EACH INPUT EQUIVALENT OF EACH OUTPUT VCC VCC 7V 180 Ω D or SHTDN YnP or YnM 5V 7V absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.
PAGE 4
SN75LVDS84A, SN65LVDS84AQ FLATLINK TRANSMITTER SLLS354E – MAY 1999 – REVISED JANUARY 2001 timing requirements tc tw Input clock period tt tsu Transition time, input signal th Hold time, data, D0 – D20 valid after CLKIN↓ (see Figure 2) Pulse duration, high-level input clock MIN NOM MAX UNIT 13.3 tc 32.4 ns 0.6 tc ns 5 ns 0.4 tc Setup time, data, D0 – D20 valid before CLKIN↓ (see Figure 2) 3 ns 1.
PAGE 5
SN75LVDS84A, SN65LVDS84AQ FLATLINK TRANSMITTER SLLS354E – MAY 1999 – REVISED JANUARY 2001 switching characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP† MAX td0 Delay time, CLKOUT↑ to serial bit position 0 td1 Delay time, CLKOUT↑ to serial bit position 1 1t 7 c * 0.2 1t 7 c ) 0.2 td2 Delay time, CLKOUT↑ to serial bit position 2 2t 7 c * 0.2 2t 7 c ) 0.2 td3 Delay time, CLKOUT↑ to serial bit position 3 3t 7 c ) 0.
PAGE 6
SN75LVDS84A, SN65LVDS84AQ FLATLINK TRANSMITTER SLLS354E – MAY 1999 – REVISED JANUARY 2001 D0 CLKIN ÏÏÏ ÏÏÏ ÏÏÏ PARAMETER MEASUREMENT INFORMATION ÏÏÏÏ ÏÏÏÏ ÏÏÏÏ ÏÏ ÏÏ CLKOUT ÎÎÎ ÎÎÎ ÏÏ ÏÏ Previous Cycle ÎÎ ÎÎ Current Cycle Y0 D0–1 D6 D5 D4 D3 D2 D1 D0 D6+1 Y1 D7–1 D13 D12 D11 D10 D9 D8 D7 D13+1 Y2 D14–1 D20 D19 D18 D17 D16 D15 D14 D20+1 Figure 1. Typical Load and Shift Sequences Dn ÏÏÏÏÏÏ ÏÏÏÏÏÏ tsu th ÏÏÏÏ ÏÏÏÏ CLKIN NOTE A: All input timing is defined at 1.
PAGE 7
SN75LVDS84A, SN65LVDS84AQ FLATLINK TRANSMITTER SLLS354E – MAY 1999 – REVISED JANUARY 2001 49.9 Ω ± 1% (2 Places) YP VOD VOC YM CL = 10 pF Max (2 Places) NOTE A: The lumped instrumentation capacitance for any single-ended voltage measurement is less than or equal to 10 pF. When making measurements at YP or YM, the complementary output is similarly loaded. (a) SCHEMATIC 100% 80% VOD(H) 0V VOD(L) 20% 0% tf tr VOC(PP) VOC(SS) VOC(SS) 0V (b) WAVEFORMS Figure 3.
PAGE 8
SN75LVDS84A, SN65LVDS84AQ FLATLINK TRANSMITTER SLLS354E – MAY 1999 – REVISED JANUARY 2001 PARAMETER MEASUREMENT INFORMATION CLKIN D0, 6, 12 D1, 7, 13 D2, 8, 14 D3, 9, 15 D18, 19, 20 All others NOTES: A. The 16-grayscale test-pattern test device power consumption for a typical display pattern. B. VIH = 2 V and VIL = 0.8 V Figure 4. 16-Grayscale Test-Pattern Waveforms tc CLKIN Even Dn Odd Dn NOTES: A. The worst-case test pattern produces nearly the maximum switching frequency for all of the LVDS outputs.
PAGE 9
SN75LVDS84A, SN65LVDS84AQ FLATLINK TRANSMITTER SLLS354E – MAY 1999 – REVISED JANUARY 2001 PARAMETER MEASUREMENT INFORMATION td7 CLKIN ÏÏ ÏÏ ÏÏ ÏÏ ÏÏ ÏÏ CLKOUT ÎÎ ÏÏÏ ÎÎ ÏÏÏ ÏÏ ÏÏ ÏÏ ÏÏ ÏÏ ÏÏ ÏÏ ÏÏ ÏÏ ÏÏ ÏÏ ÏÏ td0 Yn td1 td2 td3 td4 td5 td6 VOD(H) CLKIN CLKOUT or Yn 1.4 V 0V VOD(L) td7 td0 – td6 Figure 6. Timing Definitions + Reference ∑ Device Under Test VCO + Modulation V(t) = A sin (2 π f(mod) t) HP8665A Synthesized Signal Generator 0.
PAGE 10
SN75LVDS84A, SN65LVDS84AQ FLATLINK TRANSMITTER SLLS354E – MAY 1999 – REVISED JANUARY 2001 TYPICAL CHARACTERISTICS CLKIN Dn ten SHTDN ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ ÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌÌ Invalid Yn Valid Figure 8. Enable Time Waveforms CLKIN tdis SHTDN CLKOUT Figure 9. Disable Time Waveforms PEAK-TO-PEAK OUTPUT JITTER (NORMALIZED) vs MODULATION FREQUENCY AVERAGE SUPPLY CURRENT vs CLOCK FREQUENCY 10 Peak-To-Peak OutpuT Jitter (Normalized) I CC – Average Supply Current – mA 31 29 VCC = 3.
PAGE 11
SN75LVDS84A, SN65LVDS84AQ FLATLINK TRANSMITTER SLLS354E – MAY 1999 – REVISED JANUARY 2001 APPLICATION INFORMATION Host Graphics Controller 12-BIT RED0 RED1 RED2 RED3 NA NA GREEN0 GREEN1 GREEN2 GREEN3 NA NA BLUE0 BLUE1 BLUE2 BLUE3 NA NA H_SYNC V_SYNC ENABLE CLOCK 18-BIT RED0 RED1 RED2 RED3 RED4 RED5 GREEN0 GREEN1 GREEN2 GREEN3 GREEN4 GREEN5 BLUE0 BLUE1 BLUE2 BLUE3 BLUE4 BLUE5 H_SYNC V_SYNC ENABLE CLOCK 44 45 47 48 1 3 4 6 7 9 10 12 13 15 16 18 19 20 22 23 25 26 SN75LVDS84A/ SN65LVDS84AQ D0 Y0M D1 D2 D3
PAGE 12
SN75LVDS84A, SN65LVDS84AQ FLATLINK TRANSMITTER SLLS354E – MAY 1999 – REVISED JANUARY 2001 APPLICATION INFORMATION Host Graphics Controller 12-BIT RED0 RED1 RED2 RED3 NA NA GREEN0 GREEN1 GREEN2 GREEN3 NA NA BLUE0 BLUE1 BLUE2 BLUE3 NA NA H_SYNC V_SYNC ENABLE CLOCK 18-BIT RED0 RED1 RED2 RED3 RED4 RED5 GREEN0 GREEN1 GREEN2 GREEN3 GREEN4 GREEN5 BLUE0 BLUE1 BLUE2 BLUE3 BLUE4 BLUE5 H_SYNC V_SYNC ENABLE CLOCK 44 45 47 48 1 3 4 6 7 9 10 12 13 15 16 18 19 20 22 23 25 26 SN75LVDS84A/ SN65LVDS84AQ D0 Y0M D1 D2 D3
PAGE 13
PACKAGE OPTION ADDENDUM www.ti.
PAGE 14
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SN65LVDS84AQDGGR TSSOP DGG 48 2000 330.0 24.4 8.6 15.8 1.8 12.0 24.0 Q1 SN75LVDS84ADGGR TSSOP DGG 48 2000 330.0 24.4 8.6 15.8 1.8 12.0 24.
PAGE 15
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN65LVDS84AQDGGR TSSOP DGG 48 2000 367.0 367.0 45.0 SN75LVDS84ADGGR TSSOP DGG 48 2000 367.0 367.0 45.
PAGE 16
MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
PAGE 17
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