Datasheet

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 

SLLS268D − MARCH 1997 − REVISED JULY 2006

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D 3:21 Data Channel Expansion at up to

178.5 Mbytes/s Throughput

D Suited for SVGA, XGA, or SXGA Display

Data Transmission From Controller to

Display With Very Low EMI

D Three Data Channels and Clock

Low-Voltage Differential Channels In and

21 Data and Clock Low-Voltage TTL

Channels Out

D Operates From a Single 3.3-V Supply and

250 mW (Typ)

D 5-V Tolerant SHTDN Input

D ESD Protection Exceeds 4 kV on Bus Pins

D Packaged in Thin Shrink Small-Outline

Package (TSSOP) With 20-Mil Terminal

Pitch

D Consumes Less Than 1 mW When Disabled

D Wide Phase-Lock Input Frequency Range

31 MHz to 68 MHz

D No External Components Required for PLL

D Open-Circuit Receiver Fail-Safe Design

D Inputs Meet or Exceed the Requirements of

ANSI EIA/TIA-644 Standard

D Improved Replacement for the Nationalt

DS90C562

description

The SN75LVDS86 FlatLink receiver contains three serial-in 7-bit parallel-out shift registers, a 7× clock

synthesizer, and four low-voltage differential signaling (LVDS) line receivers in a single integrated circuit. These

functions allow receipt of synchronous data from a compatible transmitter, such as the SN75LVDS81, ’83, ’84,

or ’85, over four balanced-pair conductors, and expansion to 21 bits of single-ended low-voltage TTL (LVTTL)

synchronous data at a lower transfer rate.

When receiving, the high-speed LVDS data is received and loaded into registers at seven times (7×) the LVDS

input clock (CLKIN) rate. The data is then unloaded to a 21-bit-wide LVTTL parallel bus at the CLKIN rate. A

phase-locked loop (PLL) clock synthesizer circuit generates a 7× clock for internal clocking and an output clock

for the expanded data. The SN75LVDS86 presents valid data on the falling edge of the output clock (CLKOUT).

The SN75LVDS86 requires only four line-termination resistors for the differential inputs and little or no control.

The data bus appears the same at the input to the transmitter and output of the receiver with the data

transmission transparent to the user. The only possible user intervention is the use of the shutdown/clear

(SHTDN

) active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption. A

low level on this signal clears all internal registers to a low level.

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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

FlatLink is a trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

D17

D18

GND

D19

D20

LVDSGND

A0M

A0P

A1M

A1P

LVDSV

LVDSGND

A2M

A2P

CLKINM

CLKINP

LVDSGND

PLLGND

PLLV

PLLGND

SHTDN

CLKOUT

D16

D15

D14

GND

D13

D12

D11

D10

GND

DGG PACKAGE

(TOP VIEW)

NC − Not Connected

Summary of content (17 pages)

PAGE 1
 SLLS268D − MARCH 1997 − REVISED JULY 2006 D 3:21 Data Channel Expansion at up to D D D D D D D D D D D D 178.5 Mbytes/s Throughput Suited for SVGA, XGA, or SXGA Display Data Transmission From Controller to Display With Very Low EMI Three Data Channels and Clock Low-Voltage Differential Channels In and 21 Data and Clock Low-Voltage TTL Channels Out Operates From a Single 3.
PAGE 2
 SLLS268D − MARCH 1997 − REVISED JULY 2006 The LVDS receivers of the SN75LVDS86 include an open-circuit fail-safe design, such that when the inputs are not connected to an LVDS driver, the receiver outputs go to a low level. This occurs even when the line is differentially terminated at the receiver inputs. The SN75LVDS86 is characterized for operation over ambient free-air temperatures of 0_C to 70_C.
PAGE 3
 CLKIN ÇÇ ÇÇ ÉÉÉ ÉÉÉ Previous Cycle D0−1 D6 A1 D7−1 A2 D14−1 ÇÇ ÇÇ ÇÇ ÇÇ ÉÉ ÉÉ Current Cycle A0 CLKOUT SLLS268D − MARCH 1997 − REVISED JULY 2006 Next Cycle D5 D4 D3 D2 D1 D0 D6+1 D13 D12 D11 D10 D9 D8 D7 D13+1 D20 D19 D18 D17 D16 D15 D14 D20+1 ÉÉ ÉÉ ÇÇ ÇÇ Dn − 1 D0 ÇÇÇ ÇÇÇ ÉÉ ÉÉ ÇÇ ÇÇ Dn Dn + 1 Figure 1.
PAGE 4
 SLLS268D − MARCH 1997 − REVISED JULY 2006 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4 V Output voltage range, VO (Dxx terminals) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Input voltage range, VI: Any terminal except SHTDN .
PAGE 5
 SLLS268D − MARCH 1997 − REVISED JULY 2006 electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS VIT+ Positive-going differential input threshold voltage VIT− Negative-going differential input threshold voltage‡ VOH VOL High-level output voltage ICC IIH IIL High-level input current (SHTDN) II IOZ Input current (LVDS input terminals A and CLKIN) Low-level input current (SHTDN) MAX UNIT 100 mV mV 2.
PAGE 6
 SLLS268D − MARCH 1997 − REVISED JULY 2006 PARAMETER MEASUREMENT INFORMATION AP VID VIAP (VIAP + VIAM)/2 AM VIC VIAM Figure 2. Voltage Definitions VIC − Common-Mode Input Voltage − V 2.5 Maximum at VCC >3.15 V Maximum at VCC = 3 V 2 1.5 1 0.5 Minimum 0 0 0.1 0.2 0.3 0.4 0.5 0.6 | VID | − Differential Input Voltage − V Figure 3.
PAGE 7
 SLLS268D − MARCH 1997 − REVISED JULY 2006 PARAMETER MEASUREMENT INFORMATION CLKIN D0, D6, D12 D1, D7, D13 D2, D8, D14 D3, D9, D15 D18, D19, D20 All Others NOTE A: The 16-grayscale test-pattern test device power consumption for a typical display pattern Figure 4. 16-Grayscale Test Pattern tc CLKIN/CLKOUT Even Dn Odd Dn NOTE B: The worst-case test pattern produces nearly the maximum switching frequency for all of the LVTTL outputs. Figure 5.
PAGE 8
 SLLS268D − MARCH 1997 − REVISED JULY 2006 PARAMETER MEASUREMENT INFORMATION Tektronixt HFS9003/HFS9DG1 Stimulus System (repeating patterns of 1110111 and 0001000) An D0−D27 Device Under Test (DUT) CLKIN Tektronix Microwave Logic Multi-BERT-100RX Word Error Detector CLKOUT tc 4 t ±t 7 c (RSKM) (see Note A) tsu1 3 t t ± 7 c (RSKM) (see Note A) An and An th1 ÉÉÉÇÇ ÉÉÉÇÇ ÇÇÇÉÉ ÇÇÇÉÉ ÉÉÉÇÇ ÉÉÉÇÇ ÇÇÇÉÉ ÇÇÇÉÉ CLKIN 7× CLK (Internal) td tW CLKOUT tr < 1 ns 80% CLKIN or An ≈
PAGE 9
 SLLS268D − MARCH 1997 − REVISED JULY 2006 PARAMETER MEASUREMENT INFORMATION Reference + ∑ Device Under Test VCO + Modulation V(t) = A sin (2 π f(mod) t) HP8656B Signal Generator 0.1 MHz to 990 MHz HP8665A Synthesized Signal Generator 0.1 MHz to 4200 MHz Device Under Test Output RF OUTPUT CLKIN CLKOUT DTS2070C Digital Time Scope Input Modulation Input Figure 8.
PAGE 10
 SLLS268D − MARCH 1997 − REVISED JULY 2006 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs CLOCK FREQUENCY 80 75 I CC − Supply Current − mA VCC = 3.6 V 70 65 60 VCC = 3.3 V 55 50 45 Grayscale Data Pattern CL = 8 pF TA = 25°C VCC = 3 V 40 30 40 50 60 70 fclk − Clock Frequency − MHz Figure 11. RMS Grayscale ICC vs Clock Frequency ZERO-TO-PEAK OUTPUT JITTER vs MODULATION FREQUENCY 300 Input jitter = 750 sin (6.28 f(mod) t) ps VCC = 3.
PAGE 11
 SLLS268D − MARCH 1997 − REVISED JULY 2006 APPLICATION INFORMATION Host Cable Flat Panel Display SN75LVDS84/5 Y0M 41 8 A0M 100 Ω Y0P Y1M 40 9 39 10 A0P A1M 100 Ω Y1P Y2M 38 11 35 14 A1P A2M 100 Ω Y2P CLKOUTM 34 15 33 16 A2P CLKINM 100 Ω CLKOUTP Graphics Controller SN75LVDS86 32 17 CLKINP D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 CLKOUT 24 26 27 29 30 31 33 34 35 37 39 40 41 43 45 46 47 1 2 4 5 23 12-BIT RED0 RED1
PAGE 12
 SLLS268D − MARCH 1997 − REVISED JULY 2006 APPLICATION INFORMATION Host Cable Flat Panel Display SN75LVDS81/83 Y0M 48 8 A0M 100 Ω Y0P Y1M 47 9 46 10 A0P A1M 100 Ω Y1P Y2M 45 11 42 14 A1P A2M 100 Ω Y2P 41 15 40 16 CLKOUTM A2P CLKINM 100 Ω CLKOUTP Y3M Y3P Graphics Controller SN75LVDS86 39 17 CLKINP D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 CLKOUT 24 26 27 29 30 31 33 34 35 37 39 40 41 43 45 46 47 1 2 4 5 23 12-BIT
PAGE 13
PACKAGE OPTION ADDENDUM www.ti.
PAGE 14
PACKAGE MATERIALS INFORMATION www.ti.com 19-Jun-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN75LVDS86DGGR Package Package Pins Type Drawing TSSOP DGG 48 SPQ Reel Reel Diameter Width (mm) W1 (mm) 2000 330.0 24.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 8.6 15.8 1.8 12.0 24.
PAGE 15
PACKAGE MATERIALS INFORMATION www.ti.com 19-Jun-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN75LVDS86DGGR TSSOP DGG 48 2000 346.0 346.0 41.
PAGE 16
MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
PAGE 17
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