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SLAS328 − SEPTEMBER 2001

   

    

www.ti.com

FEATURES

TAS5010 + TAS5100 TDAA System − High

Quality Digital Audio Amplification

D 96-dB Dynamic Range (TAS5010 Device)

D 93-dB Dynamic Range (TAS5010 & TAS5100

System Measured at Speaker Terminals)

D THD+N < 0.08% (1 kHz, 1 to 30W RMS into 6 Ω)

D Power Efficiency Is 90% Into 8-Ω Load

D 16-, 20-, or 24-Bit Input Data

D 44.1-kHz, 48-kHz, 88.2-kHz, 96-kHz, 176.4-kHz,

192-kHz Sampling Rates

D Economical 48-Pin TQFP Package

D Lower-Jitter Internal PLL

D 3.3-V Power Supply

D Mute

D Clicks and Pops Reduction (Patent Pending)

APPLICATIONS

DVD-Audio

D Home Theater

D Car Audio Amplifiers and Head Units

D Internet Music Appliance

D Mini/Micro Component Systems

DESCRIPTION

The true digital audio amplifier (TDAA) is a new

paradigm in digital audio. One TDAA system consists of

the TAS5010 PCM-PWM modulator device + a

TAS5100 PWM power output device. This system

accepts a serial PCM digital audio stream and converts

it to a 3.3-V PWM audio stream (TAS5010). The

TAS5100 device then provides a large-signal PWM

output. This digital PWM signal is then demodulated

providing power output for driving loudspeakers. This

patented technology provides low-cost, high-quality,

high- efficiency digital audio applicable to many audio

systems developed for the digital age. The TAS5010 is

an innovative, cost-effective, high-performance 24-bit

stereo PCM-PWM modulator based on Equibit

technology. It has a wide variety of serial input options

including right-justified (16, 20, or 24 bits), IIS (16, 20,

or 24 bits), left-justified (16 bits), or DSP (16 bits) data

formats. It is fully compatible with AES standard

sampling rates of 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz,

176.4 kHz, and 192 kHz. The TAS5010 also provides a

de-emphasis function for 44.1-kHz and 48-kHz

sampling rates.

TAS5010

TAS5100

Left

• Volume

• EQ

• DRC

• Bass

• Treble

• Serial Audio Input Port

• Internal PLL

• Equibit Modulator

• Up to 192-kHz Sampling

• TAS3001

• DSP

• S/PDIF

• 1394

Digital Audio

• H-Bridges

Power Devices

TAS5100

Right

L-C

Filter

L-C

Filter

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Equibit is a trademark of Toccata Technology ApS, Denmark.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Summary of content (21 pages)

PAGE 1
SLAS328 − SEPTEMBER 2001 FEATURES D TAS5010 + TAS5100 TDAA System − High D D D D D D D D D D D DESCRIPTION Quality Digital Audio Amplification 96-dB Dynamic Range (TAS5010 Device) 93-dB Dynamic Range (TAS5010 & TAS5100 System Measured at Speaker Terminals) THD+N < 0.08% (1 kHz, 1 to 30W RMS into 6 Ω) Power Efficiency Is 90% Into 8-Ω Load 16-, 20-, or 24-Bit Input Data 44.1-kHz, 48-kHz, 88.2-kHz, 96-kHz, 176.
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SLAS328 − SEPTEMBER 2001 terminal assignments AVDD1 XTL_IN XTL_OUT OSC_CAP AVSS1 DEM_EN DEM_SEL FTEST STEST DBSPD MUTE DVSS3_L 48-Pin TQFP PACKAGE (TOP VIEW) 48 47 46 45 44 43 42 41 40 39 38 37 MCLK_IN AVDD2 PLL_FLT_OUT PLL_FLT_RET AVSS2 NC RESET PDN VALID_R M_S NC DVDD1 1 36 2 35 3 34 4 33 5 32 6 31 7 30 8 29 9 28 10 27 11 26 12 25 DVDD3_L PWM_AP_L PWM_AM_L NC NC DVDD2 DVSS2 PWM_AP_R PWM_AM_R NC NC DVDD3_R DVSS1 DVDD1 DVSS1 MCLK_OUT SCLK LRCLK SDIN MOD2 MOD1 MOD0 VALI
PAGE 3
SLAS328 − SEPTEMBER 2001 PLL/Clock Generator LRCLK Serial Audio Port SCLK OSC_CAP XTL_OUT XTL_IN MCLK_OUT VALID_R VALID_L MCLK_IN PLL_FLT_OUT PLL_FLT_RET functional block diagram OSC Digital Interpolation Filter Equibit Modulator PWM_AP_L PWM_AM_L Buffer PWM_AP_R PWM_AM_R SDIN Control Section DVDD1 DVSS1 DVDD2 DVSS2 DVDD3_L DVSS3_L DVDD3_R DVSS3_R AVDD1 AVSS1 AVDD2 AVSS2 STEST DBSPD M_S FTEST PDN RESET MUTE DEM_EN DEM_SEL MOD2 MOD1 MOD0 Audio Port Configuration AVAI
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SLAS328 − SEPTEMBER 2001 Terminal Functions TERMINAL NAME I/O DESCRIPTION AVDD1 48 I Analog supply for oscillator AVDD2 2 I Analog supply for PLL AVSS1 44 I Analog ground for oscillator AVSS2 5 I Analog ground for PLL DBSPD 39 I Indicates sample rate is double speed (88.2 kHz or 96 kHz), active high DEM_EN 43 I De-emphasis enable, active high DEM_SEL 42 I De-emphasis select (0 = 44.
PAGE 5
SLAS328 − SEPTEMBER 2001 functional description serial audio port The serial audio port consists of a shift clock (SCLK pin), a left/right frame synchronization clock (LRCLK pin), and a data input (SDIN pin). The serial audio port supports standard serial PCM formats (Fs = 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4kHz, or 192kHz) stereo. See serial interface formats section. system clocks—master mode and slave mode The TAS5010 allows multiple system clocking schemes.
PAGE 6
SLAS328 − SEPTEMBER 2001 functional description (continued) digital interpolation filter The 24-bit high-performance linear phase FIR interpolation filter up-samples the input digital data at a rate of 2 times (quad speed mode = 176.4kHz or 192kHz), 4 times (double speed mode = 88.2 kHz or 96 kHz), or 8 times (normal mode = 44.1 kHz or 48 kHz) the incoming sample rate. This filter provides very low pass-band ripple and optimized time domain transient response for accurate music reproduction.
PAGE 7
SLAS328 − SEPTEMBER 2001 functional description (continued) reset The reset signal for the TAS5010 must be applied whenever toggling the M_S, DBSPD signal. This reset is asynchronous. See Figure 3 for reset timing. To initiate the reset sequence the RESET pin is asserted low. As long as the pin is held low the chip is in the reset state. During this reset time the PWM outputs are hard-muted (P-outputs held low and M-outputs held high) and the PWM outputs valid pins (VALID_L. VALID_R) are held low.
PAGE 8
SLAS328 − SEPTEMBER 2001 functional description (continued) 10 µs Maximum MUTE 5 ms max Initialization VALID_L VALID_R PWM Outputs PWM_AP_L PWM_AM_L PWM_AP_R PWM_AM_R 50−50 Duty Cycle (P, M Complementary) Inactive State Normal State (P, M Complementary) Figure 5. Mute Timing double speed Double-speed mode is used to support sampling rates of 88.2 kHz and 96 kHz.
PAGE 9
SLAS328 − SEPTEMBER 2001 functional description (continued) de-emphasis selection De-emphasis selection is accomplished by using the DEM_SEL and DEM_EN pins. See Table 3 for de-emphasis selection description. Table 3. De-Emphasis Selection DEM_SEL DEM_EN 0 0 De-emphasis disabled DESCRIPTION 0 1 De-emphasis enabled for Fs = 44.1 kHz 1 1 De-emphasis enabled for Fs = 48 kHz 1 0 Forbidden modey. Do not use.
PAGE 10
SLAS328 − SEPTEMBER 2001 functional description (continued) MSB first, right-justified (for 16, 20, 24 bits) SCLK LRCLK = fs X SDIN MSB LSB X Left Channel MSB LSB Right Channel Figure 7. MSB First Right Justified Note the following characteristics of this protocol: − Left channel is received when LRCLK is high. − Right channel is received when LRCLK is low. − SDIN is sampled at the rising edge of SCLK.
PAGE 11
SLAS328 − SEPTEMBER 2001 functional description (continued) MSB left-justified serial interface format (for 16 bits) SCLK LRCLK = fs SDIN MSB LSB MSB LSB Left Channel Right Channel Figure 9. MSB Left-Justified Serial Interface Format Note the following characteristics of this protocol: − Left channel is received when LRCLK is high. − Right channel is received when LRCLK is low. − SDIN is sampled at the rising edge of SCLK.
PAGE 12
SLAS328 − SEPTEMBER 2001 absolute maximum ratings over operating free-air temperature (unless otherwise noted)† Analog supply voltage range, AVDD1, AVDD2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.2 V Digital power supply voltage, DVDD1, DVDD2, DVDD3_L, DVDD3_R . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 4.2 V Digital input voltage, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 13
SLAS328 − SEPTEMBER 2001 TAS5010/TAS5100 system performance measured at the speaker terminals See application note, literature number SLAA117. switching characteristics, TA = 25°C, DVDD1 = DVDD2 = DVDD3_L = DVDD3_R = AVDD1 = AVDD2 = 10% 3.3 V ±10% serial audio ports slave mode PARAMETER MIN TYP MAX UNIT 12.
PAGE 14
SLAS328 − SEPTEMBER 2001 PARAMETER MEASUREMENT INFORMATION SCLK ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ tsu(SDIN) th(SDIN) SDIN Figure 11. Right-Justified, IIS, Left-Justified Serial Protocol Timing SCLK tsu(LRCLK) LRCLK NOTE: Serial data is sampled with the rising edge of SCLK (setup time = 20 ns and hold time = 10 ns) Figure 12. Right, Left, and IIS Serial Mode Timing Requirement SCLK LRCLK (Output) t(MSD) t(MLRD) MCLK (Output) Figure 13.
PAGE 15
SLAS328 − SEPTEMBER 2001 PARAMETER MEASUREMENT INFORMATION SCLK LRCLK tw(FSHIGH) 64 SCLKs 16-Bit Left Channel Data SDIN 16-Bit Left Channel Data 32-Bit Ignore 16-Bit Left Channel Data Figure 15. DSP Serial Port Expanded Timing SCLK ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ tsu(SDIN) = 20 ns th(SDIN) = 10 ns SDIN NOTE: Serial data is sampled with the falling edge of SCLK (setup time = 20 ns and hold time = 10 ns) Figure 16. DSP Absolute Timing Requirement www.ti.
PAGE 16
SLAS328 − SEPTEMBER 2001 APPLICATION INFORMATION TAS5010 PLL_FLT_RET PWM_AP_L PWM_AM_L C2† C1† TAS5100 H-Bridge R1† PLL_FLT_OUT VALID_L RESET DEM_SEL Audio Source Clock Generator 3.3 V DIG DEM_EN DBSPD SDIN PWM_AP_R PWM_AM_R LRCLK SCLK MCLK_IN MOD0 RESET System Controller MOD1 MOD2 RESET M_S MUTE PDN XTL_IN FTEST STEST † See application note, literature number SLAA117 for values 16 VALID_R TAS5100 H-Bridge www.ti.
PAGE 17
SLAS328 − SEPTEMBER 2001 MECHANICAL DATA PFB (S-PQFP-G48) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 36 0,08 M 25 37 24 48 13 0,13 NOM 1 12 5,50 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,25 0,05 MIN 0°−ā 7° 1,05 0,95 Seating Plane 1,20 MAX 0,75 0,45 0,08 4073176 / B 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 www.ti.
PAGE 18
PACKAGE OPTION ADDENDUM www.ti.
PAGE 19
PACKAGE MATERIALS INFORMATION www.ti.com 29-Jul-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device TAS5010PFBR Package Package Pins Type Drawing TQFP PFB 48 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 16.4 Pack Materials-Page 1 9.6 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 9.6 1.5 12.0 16.
PAGE 20
PACKAGE MATERIALS INFORMATION www.ti.com 29-Jul-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TAS5010PFBR TQFP PFB 48 1000 346.0 346.0 33.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.