Datasheet

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FEATURES

TAS5086

www.ti.com

................................................................................................................................................... SLES131C – FEBRUARY 2005 – REVISED JUNE 2008

PurePath Digital™ AUDIO SIX-CHANNEL PWM PROCESSOR

– Full Six-Channel Input and Output Mapping

• Audio Input/Output – Selectable DC Blocking Filters

– Automatic Master Clock Rate and Data • PWM Processing

Sample Rate Detection

– 8 × Oversampling With Fourth-Order Noise

– Four Serial Audio Inputs (Eight Channels) Shaping at 44.1, 48 kHz; 4 × Oversampling

at 88.2, 96 kHz; 2 × Oversampling at 176.4,

– Support for 32-, 44.1-, 48-, 88.2-, 96-, 176.4-,

192 kHz; and 12 × Oversampling at 32 kHz

and 192-kHz Sampling Rates

– ≥ 105-dB Dynamic Range

– Data Formats: 16-, 20-, or 24-Bit Input Data;

(TAS5086+TAS5186)

Left-Justified, Right-Justified, and I

– THD < 0.06% (TAS5086 Only)

– 64- or 48-f

Bit-Clock Rate

– 20-Hz – 20-kHz Flat Noise Floor for 44.1-, 48-,

– 128-, 192-, 256-, 384-, and 512-f

Master

88.2-, 96-, 176.4- and 192-kHz Data Rates

Clock Rates (Up to a Maximum of 50 MHz)

– Digital De-Emphasis for 32-kHz, 44.1-kHz

– Six PWM Audio Output Channels

and 48-kHz Data Rates

– Any Output Channel Can be Mapped to Any

– Intelligent AM Interference Avoidance

Output Pin

System Provides Clear AM Reception

– Supports Single-Ended and Bridge-Tied

– Optimized PWM Sequence for Click- and

Loads

Popless Start and Stop

– I

S Serial Audio Output

– Optimized PWM Sequence for Charging of

• Audio Processing

AC-Coupling Capacitors in Single-Ended

– Volume Control Range of 48 dB to – 100 dB

Configurations

– Master Volume Control from 24 dB to – 100

– Adjustable Modulation Limit From 93.8% to

dB in 0.5-dB Increments

99.2%

– Six Individual Channel Volume Controls

• General Features

With 24-dB to – 100-dB Attenuation in

– Automated Operation With Easy-to-Use

0.5-dB Increments

Control Interface

– Serial Output Can Be Produced by

– I

C Serial Control Slave Interface

Downmix of 5.1-Channel Input or Fourth

– Control Interface Operational Without

Serial Input

MCLK

– 5.1-Channel Downmix to 2.1 or 3.1 PWM

– Single 3.3-V Power Supply

Output Speaker System

– 38-Pin TSSOP Package

– Integrated Bass Management

– Two Programmable Biquads in Subwoofer

Channel

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2 PurePath Digital is a trademark of Texas Instruments.

3 All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (48 pages)

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TAS5086 www.ti.com ................................................................................................................................................... SLES131C – FEBRUARY 2005 – REVISED JUNE 2008 PurePath Digital™ AUDIO SIX-CHANNEL PWM PROCESSOR FEATURES 1 • Audio Input/Output – Automatic Master Clock Rate and Data Sample Rate Detection – Four Serial Audio Inputs (Eight Channels) – Support for 32-, 44.1-, 48-, 88.2-, 96-, 176.
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TAS5086 SLES131C – FEBRUARY 2005 – REVISED JUNE 2008 ................................................................................................................................................... www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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TAS5086 www.ti.com ................................................................................................................................................... SLES131C – FEBRUARY 2005 – REVISED JUNE 2008 DVDD DVSS DVSS_ESD VR_DIG VR_ANA VR_OSC AVDD AVSS_PLL VREG_EN SDIN1 SDIN2 SDIN3 SDIN4 1 LF Power Supply SCL MUX PWM1 MUX PWM2 MUX PWM3 MUX PWM4 MUX PWM5 MUX PWM6 6 Serial Data Interface R’ Chan.
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TAS5086 SLES131C – FEBRUARY 2005 – REVISED JUNE 2008 ................................................................................................................................................... www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) Supply voltage Input voltage DVDD and DVD_ESD –0.3 V to 3.6 V AVDD –0.3 V to 3.6 V 3.3-V-digital input –0.5 V to DVDD + 0.5 V 5-V-tolerant (2) digital input –0.
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TAS5086 www.ti.com ................................................................................................................................................... SLES131C – FEBRUARY 2005 – REVISED JUNE 2008 Serial Audio Port Serial audio port slave mode over recommended operating conditions (unless otherwise noted) PARAMETER fSCLKIN SCLK input frequency TEST CONDITIONS MIN CL = 30 pF, SCLK = 64 fS 2.048 TYP MAX UNIT 12.
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TAS5086 SLES131C – FEBRUARY 2005 – REVISED JUNE 2008 ................................................................................................................................................... www.ti.com TAS5086 Bus-Related Characteristics of the SDA and SCL I/O Stages for F/S-Mode I 2C-Bus Devices All values are referred to VIHmin and VILmax (see TAS5086 Pin-Related Characteristics of the SDA and SCL I/O Stages for F/S-Mode I2C-Bus Devices).
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TAS5086 www.ti.com ................................................................................................................................................... SLES131C – FEBRUARY 2005 – REVISED JUNE 2008 Recommended I2C Pullup Resistors It is recommended that the I2C pullup resistors RP be 3.3 kΩ (see Figure 4). If a series resistor is in the circuit (see Figure 5), then the series resistor RS should be less than or equal to 300 Ω.
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TAS5086 SLES131C – FEBRUARY 2005 – REVISED JUNE 2008 ................................................................................................................................................... www.ti.
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TAS5086 www.ti.com ................................................................................................................................................... SLES131C – FEBRUARY 2005 – REVISED JUNE 2008 Table 1. TERMINAL FUNCTIONS (continued) TERMINAL NAME NO. I/O (1) 5-V TERMINATION (2) TOLERANT Pullup Power down, active-low. PDN powers down all logic, stops all clocks, and performs a soft stop whenever a logic low is applied.
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TAS5086 SLES131C – FEBRUARY 2005 – REVISED JUNE 2008 ................................................................................................................................................... www.ti.com DETAILED DESCRIPTION POWER SUPPLY The TAS5086 power-supply section contains regulators that provide analog and digital regulated power for various sections of the TAS5086.
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TAS5086 www.ti.com ................................................................................................................................................... SLES131C – FEBRUARY 2005 – REVISED JUNE 2008 SERIAL DATA INTERFACE Serial data is input on SDIN1, SDIN2, SDIN3, and SDIN4. The PWM outputs and downmix are derived from SDIN1, SDIN2, and SDIN3. SDIN4 is a selectable pass-through signal that is available at SDOUT as an I2S output. The TAS5086 accepts 32-, 44.1-, 48-, 88.2-, 96-, 176.
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TAS5086 SLES131C – FEBRUARY 2005 – REVISED JUNE 2008 ................................................................................................................................................... www.ti.com Channel-6 Processing Section Channel 6 has processing features that are directly applicable to the subwoofer channel. Bass Management 0x21 Ch 1–5 Ch 6 Sub 10 dB S MUX 0x0D 0x23 GainCompensated Biquad 0x24 LowPass Biquad VOL BQ1 BQ2 BQ1 (G) From Downmix (L’+R’)/2 B0050-01 Figure 7.
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TAS5086 www.ti.com ................................................................................................................................................... SLES131C – FEBRUARY 2005 – REVISED JUNE 2008 It also has individual channel dc-blocking filters that are enabled by default. Individual channel de-emphasis filters for 32, 44.1, and 48 kHz are included and can be enabled and disabled. There is also a two-channel downmix result that can be output on SDOUT (I2S format).
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TAS5086 SLES131C – FEBRUARY 2005 – REVISED JUNE 2008 ................................................................................................................................................... www.ti.com Power Stage TAS5086 VPP PWM PSU IN OUT GND S0270-01 Figure 9. SE Filter Configuration The TAS5086 supports two mechanisms for controlling the split-capacitor midpoint.
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TAS5086 www.ti.com ................................................................................................................................................... SLES131C – FEBRUARY 2005 – REVISED JUNE 2008 Extra Half-Bridge TAS5086 VPP PWM ValidSS IN OUT RES GND PSU Power Stage VPP IN Valid OUT RES GND S0271-01 Figure 10.
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TAS5086 SLES131C – FEBRUARY 2005 – REVISED JUNE 2008 ................................................................................................................................................... www.ti.com Reset Timing (RESET) Control-signal parameters over recommended operating conditions (unless otherwise noted) Earliest time that M-State could be exited RESET tw(RESET) M-State tr(I2C_ready) tr(run) tr(DMSTATE) < 200 ns Determine SCLK rate and MCLK ratio. Enable via I2C.
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TAS5086 www.ti.com ...................................................................................................................................................
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TAS5086 SLES131C – FEBRUARY 2005 – REVISED JUNE 2008 ................................................................................................................................................... www.ti.com SERIAL INTERFACE CONTROL AND TIMING I2S TIMING I2S timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCLK is low for the left channel and high for the right channel. A bit clock running at 64 fS is used to clock in the data.
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TAS5086 www.ti.com ...................................................................................................................................................
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TAS5086 SLES131C – FEBRUARY 2005 – REVISED JUNE 2008 ................................................................................................................................................... www.ti.com 2-Channel Left-Justified Stereo Input 32 Clks 32 Clks Left Channel Right Channel LRCLK SCLK SCLK MSB 24-Bit Mode 23 22 LSB 9 8 5 4 5 4 1 0 1 0 1 0 MSB LSB 23 22 9 8 5 4 19 18 5 4 1 0 15 14 1 0 1 0 20-Bit Mode 19 18 16-Bit Mode 15 14 T0034-02 Figure 18.
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TAS5086 www.ti.com ................................................................................................................................................... SLES131C – FEBRUARY 2005 – REVISED JUNE 2008 Right-Justified Right-justified (RJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 64 fS is used to clock in the data.
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TAS5086 SLES131C – FEBRUARY 2005 – REVISED JUNE 2008 ................................................................................................................................................... www.ti.
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TAS5086 www.ti.com ................................................................................................................................................... SLES131C – FEBRUARY 2005 – REVISED JUNE 2008 SDA R/ A W 7-Bit Slave Address 7 6 5 4 3 2 1 0 8-Bit Register Address (N) 7 6 5 4 3 2 1 0 8-Bit Register Data For Address (N) A 7 6 5 4 3 2 1 8-Bit Register Data For Address (N) A 0 7 6 5 4 3 2 1 A 0 SCL Start Stop T0035-01 Figure 22.
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TAS5086 SLES131C – FEBRUARY 2005 – REVISED JUNE 2008 ................................................................................................................................................... www.ti.com Start Condition Acknowledge A6 A5 A4 A3 A2 A1 A0 Acknowledge R/W ACK A7 A6 A5 2 A4 A3 A2 A1 Acknowledge A0 ACK D7 D6 D5 Subaddress I C Device Address and Read/Write Bit D4 D3 D2 D1 D0 ACK Stop Condition Data Byte T0036-01 Figure 23.
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TAS5086 www.ti.com ................................................................................................................................................... SLES131C – FEBRUARY 2005 – REVISED JUNE 2008 memory address to be read. As a result, the read/write bit is set to a 0. After receiving the TAS5086 address and the read/write bit, the TAS5086 responds with an acknowledge bit.
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TAS5086 SLES131C – FEBRUARY 2005 – REVISED JUNE 2008 ................................................................................................................................................... www.ti.
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TAS5086 www.ti.com ................................................................................................................................................... SLES131C – FEBRUARY 2005 – REVISED JUNE 2008 Default values are in bold, table values "X" equals don't care and table values "–" equals an expansion of the table for detailed description of the respective bit. SUBADDRESS NO.
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TAS5086 SLES131C – FEBRUARY 2005 – REVISED JUNE 2008 ................................................................................................................................................... www.ti.com DEVICE ID REGISTER (0x01) The device ID register contains the ID code for the TAS5086. Table 3.
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TAS5086 www.ti.com ................................................................................................................................................... SLES131C – FEBRUARY 2005 – REVISED JUNE 2008 Table 5.
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TAS5086 SLES131C – FEBRUARY 2005 – REVISED JUNE 2008 ................................................................................................................................................... www.ti.com SYSTEM CONTROL REGISTER 2 (0x05) Bit D6 is a control bit and bit D5 is a configuration bit. When bit D6 is set low, the system starts playing; otherwise, the outputs are shut down. Bit D5 defines the configuration of the system, i.e.
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TAS5086 www.ti.com ................................................................................................................................................... SLES131C – FEBRUARY 2005 – REVISED JUNE 2008 VOLUME CONTROL REGISTER (0x0E) Bit D7: Reserved = 1 Bit D6: If 0, then biquad 1 (BQ1) volume compensation part only is disabled (default). If 1, then BQ1 volume compensation is enabled. Bit D5: If 0, disable 38-kHz input sample rate detection (38 kHz should be set manually by the microprocessor).
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TAS5086 SLES131C – FEBRUARY 2005 – REVISED JUNE 2008 ................................................................................................................................................... www.ti.com PWM START REGISTER (0x18) Bits D7 and D6: Define which start sequence is used, either low-Z or mid-Z. Not all power stages are compatible with mid-Z; double-check the power-stage data sheet.
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TAS5086 www.ti.com ................................................................................................................................................... SLES131C – FEBRUARY 2005 – REVISED JUNE 2008 SURROUND REGISTER (0x19) Defines which channels should be running in the 2.0/2.1 mode. The channels having their surround register set (HIGH) belong to shutdown group 1. They are associated with VALID1.
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TAS5086 SLES131C – FEBRUARY 2005 – REVISED JUNE 2008 ................................................................................................................................................... www.ti.com SPLIT-CAPACITOR CHARGE PERIOD REGISTER (0x1A) This register should contain the code that closely matches the external single-ended split-capacitor charge period. The TAS5086 waits for this period of time before starting the PWM signals. This helps reduce pops and clicks.
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TAS5086 www.ti.com ................................................................................................................................................... SLES131C – FEBRUARY 2005 – REVISED JUNE 2008 OSCILLATOR TRIM REGISTER (0x1B) The TAS5086 PWM processor contains an internal oscillator for PLL reference. This reduces system cost because an external reference is not required. A trim resitor value of 18 kΩ is recomended.
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TAS5086 SLES131C – FEBRUARY 2005 – REVISED JUNE 2008 ................................................................................................................................................... www.ti.com Table 16.
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TAS5086 www.ti.com ................................................................................................................................................... SLES131C – FEBRUARY 2005 – REVISED JUNE 2008 Table 17.
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TAS5086 SLES131C – FEBRUARY 2005 – REVISED JUNE 2008 ................................................................................................................................................... www.ti.com DOWNMIX INPUT MULTIPLEXER REGISTER (0x21) Bits D31–D16: Unused Bits D15–D13: For this description, see Figure 6.
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TAS5086 www.ti.com ................................................................................................................................................... SLES131C – FEBRUARY 2005 – REVISED JUNE 2008 Table 18.
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TAS5086 SLES131C – FEBRUARY 2005 – REVISED JUNE 2008 ................................................................................................................................................... www.ti.com Table 21.
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TAS5086 www.ti.com ................................................................................................................................................... SLES131C – FEBRUARY 2005 – REVISED JUNE 2008 Table 22.
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TAS5086 SLES131C – FEBRUARY 2005 – REVISED JUNE 2008 ................................................................................................................................................... www.ti.com APPENDIX A. TAS5086 APPLICATIONS For detailed application information, see the TAS5086-5186V6EVM application report (SLEA054).
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TAS5086DBTR Package Package Pins Type Drawing TSSOP DBT 38 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 16.4 Pack Materials-Page 1 6.9 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 10.2 1.8 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TAS5086DBTR TSSOP DBT 38 2000 367.0 367.0 38.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.