Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLinear ICsLinear IC - Audio amplifier 2-channel (stereo) Class D HTSSOP 56

TAS5112A

SLES094B - OCTOBER 2003 - REVISED JUNE 2008

DIGITAL AMPLIFIER POWER STAGE

FEATURES

D 50 W per Channel (BTL) Into 6 Ω (Stereo)

D 95-dB Dynamic Range With TAS5026

D Less Than 0.1% THD+N (1 W RMS Into 6 Ω)

D Less Than 0.2% THD+N (50 W RMS into 6 Ω)

D Power Efficiency Typically 90% Into 6-Ω Load

D Self-Protecting Design (Undervoltage,

Overtemperature and Short Conditions) With

Error Reporting

D Internal Gate Drive Supply Voltage Regulator

D EMI Compliant When Used With

Recommended System Design

APPLICATIONS

D DVD Receiver

D Home Theatre

D Mini/Micro Component Systems

D Internet Music Appliance

DESCRIPTION

The TAS5112A is a high-performance, integrated stereo

digital amplifier power stage designed to drive 6-Ω

speakers at up to 50 W per channel. The device

incorporates TI’s PurePath Digitalt technology and is

used with a digital audio PWM processor (TAS50XX) and

a simple passive demodulation filter to deliver high-quality,

high-efficiency, true-digital audio amplification.

The efficiency of this digital amplifier is typically 90%,

reducing the size of both the power supplies and heatsinks

needed. Overcurrent protection, overtemperature

protection, and undervoltage protection are built into the

TAS5112A, safeguarding the device and speakers against

fault conditions that could damage the system.

- Output Power - W

100m

= 6 Ω

= 75°C

1 10 100

0.01

0.1

THD+N - Total Harmonic Distortion + Noise - %

THD + NOISE vs OUTPUT POWER

f - Frequency - Hz

20 100 1k 10k

THD+N - Total Harmonic Distortion + Noise - %

0.001

0.1

20k

= 6 Ω

= 75°C

0.01

THD + NOISE vs FREQUENCY

= 50 W

= 1 W

= 10 W

PurePath Digital and PowerPAD are trademarks of Texas Instruments.

Other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Products

conform to specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

www.ti.com

Summary of content (30 pages)

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TAS5112A www.ti.com SLES094B - OCTOBER 2003 - REVISED JUNE 2008 TM DIGITAL AMPLIFIER POWER STAGE FEATURES D 50 W per Channel (BTL) Into 6 Ω (Stereo) D 95-dB Dynamic Range With TAS5026 D Less Than 0.1% THD+N (1 W RMS Into 6 Ω) D Less Than 0.
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TAS5112A www.ti.com SLES094B - OCTOBER 2003 - REVISED JUNE 2008 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. GENERAL INFORMATION Terminal Assignment The TAS5112A is offered in a thermally enhanced 56-pin TSSOP DFD (thermal pad is on the top) and DCA (thermal pad is on the bottom), shown as follows.
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TAS5112A www.ti.com SLES094B - OCTOBER 2003 - REVISED JUNE 2008 Absolute Maximum Ratings Package Dissipation Ratings over operating free-air temperature range unless otherwise noted(1) PACKAGE RθJC (°C/W) RθJA (°C/W) –0.3 V to 4.2 V 56-pin DFD TSSOP 1.14 See Note 4 GVDD TO GND 33.5 V 56-pin DCA TSSOP 1.14 See Note 4 PVDD_X TO GND (dc voltage) 33.5 V TAS5112A DVDD TO DGND PVDD_X TO GND (spike voltage(2)) OUT_X TO GND (dc voltage) UNITS 48 V 33.
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TAS5112A www.ti.
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TAS5112A www.ti.com SLES094B - OCTOBER 2003 - REVISED JUNE 2008 FUNCTIONAL BLOCK DIAGRAM BST_A GREG PVDD_A Gate Drive PWM_AP PWM Receiver OUT_A Timing Control Gate Drive GND Protection A BST_B RESET GREG PVDD_B Protection B Gate Drive PWM_BP PWM Receiver OUT_B Timing Control Gate Drive To Protection Blocks GND DREG DREG GVDD OTW GREG OT Protection SD GREG GREG DREG GREG UVP DREG_RTN DREG_RTN This diagram shows one channel.
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TAS5112A www.ti.com SLES094B - OCTOBER 2003 - REVISED JUNE 2008 RECOMMENDED OPERATING CONDITIONS (1) MIN TYP MAX UNIT DVDD Digital supply Relative to DGND 3 3.3 3.6 V GVDD Supply for internal gate drive and logic regulators Relative to GND 16 29.5 30.5 V PVDD_x Half-bridge supply Relative to GND, RL= 6 Ω to 8 Ω 0 29.5 30.5 V TJ Junction temperature 125 _C (1) 0 It is recommended for DVDD to be connected to DREG via a 100-Ω resistor. ELECTRICAL CHARACTERISTICS PVDD_X = 29.
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TAS5112A www.ti.com SLES094B - OCTOBER 2003 - REVISED JUNE 2008 ELECTRICAL CHARACTERISTICS PVDD_x = 29.5 V, GVDD = 29.5 V, DVDD connected to DREG via a 100-Ω resistor, RL = 6 Ω, 8X fs = 384 kHz, unless otherwise noted TYPICAL SYMBOL PARAMETER TEST CONDITIONS TA=25°C OVER TEMPERATURE TCase= 75°C TA=40°C TO 85°C UNITS MIN/TYP/ MAX 6.9 V Min 7.
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TAS5112A www.ti.com SLES094B - OCTOBER 2003 - REVISED JUNE 2008 SYSTEM CONFIGURATION USED FOR CHARACTERIZATION Gate-Drive Power Supply External Power Supply H-Bridge Power Supply TAS5112ADFD 1 1 µF 56 GND GND 2 55 GND GVDD 3 GREG 4 53 OTW PVDD_D SD_CD PVDD_D SD_AB OUT_D PWM_DP OUT_D 5 6 ERR_RCVY 49 PWM_DM 11 12 100 nF PWM PROCESSOR TAS5026 13 14 PWM_AP_2 PWM_CP M3 PVDD_C M2 BST_C M1 BST_B PWM_BP PVDD_B PWM_BM OUT_B RESET_AB OUT_B PWM_AM GND PWM_AP GND 8 † 1.
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TAS5112A www.ti.com SLES094B - OCTOBER 2003 - REVISED JUNE 2008 TYPICAL CHARACTERISTICS AND SYSTEM PERFORMANCE OF TAS5112ADFD EVM WITH TAS5026 PWM PROCESSOR TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY NOISE AMPLITUDE vs FREQUENCY 0 RL = 6 Ω TC = 75°C RL = 6Ω FFT = -60 dB TC = 75°C TAS5026 Front End Device −20 PO = 50 W −40 Noise Amplitude - dBr THD+N - Total Harmonic Distortion + Noise - % 1 0.1 PO = 10 W PO = 1 W 0.01 −60 −80 −100 −120 −140 0.
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TAS5112A www.ti.
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TAS5112A www.ti.
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TAS5112A www.ti.com From PWM Processor SLES094B - OCTOBER 2003 - REVISED JUNE 2008 Figure 10.
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TAS5112A www.ti.com SLES094B - OCTOBER 2003 - REVISED JUNE 2008 THEORY OF OPERATION POWER SUPPLIES The power device only requires two supply voltages, GVDD and PVDD_X. GVDD is the gate drive supply for the device, regulated internally down to approximately 12 V, and decoupled with regards to board GND on the GREG pins through an external capacitor. GREG powers both the low side and high side via a bootstrap step-up conversion. The bootstrap supply is charged after the first low-side turn-on pulse.
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TAS5112A www.ti.com SLES094B - OCTOBER 2003 - REVISED JUNE 2008 In practice this means that the DVDD-to-PWM processor (front-end) should be stable and initialization should be completed before RESET is de-asserted to the back end. The device can be recovered by toggling RESET low and then high, after all errors are cleared.
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TAS5112A www.ti.com SLES094B - OCTOBER 2003 - REVISED JUNE 2008 Timing and Function Table 3. Output Mode Selection The function of the autorecovery circuit is as follows: 1. An error event occurs and sets the protection latch (output stage goes Hi-Z). 2. The counter is started. 3. After n/2 cycles, the protection latch is cleared but the output stage remains Hi-Z (identical to pulling RESET low). 4. After n cycles, operation is resumed (identical to pulling RESET high) (n = 512).
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TAS5112A www.ti.com SLES094B - OCTOBER 2003 - REVISED JUNE 2008 should remain stable within the range of peak current seen at maximum output power and deliver at least 5 µH of inductance at 15 A. If this rule is observed, the TAS5112A does not have distortion issues due to the output inductors, and overcurrent conditions do not occur due to inductor saturation in the output filter. Another parameter to be considered is the idle current loss in the inductor.
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TAS5112A www.ti.com SLES094B - OCTOBER 2003 - REVISED JUNE 2008 Table 5. Case 2 (2 × 50 W Unclipped Into 6 Ω, Channels in Separate Packages) (1) Heatsink thermal resistance is generally predicted by the heatsink vendor, modeled using a continuous flow dynamics (CFD) model, or measured. Thus, for a single monaural IC, the system RθJA = RθJC + thermal grease resistance + heatsink resistance. Table 4, Table 5, and Table 6 indicate modeled parameters for one or two TAS5112A ICs on a single heatsink.
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TAS5112A www.ti.com SLES094B - OCTOBER 2003 - REVISED JUNE 2008 DCA THERMAL INFORMATION The thermally enhanced DCA package is based on the 56-pin HTSSOP, but includes a thermal pad (see Figure 14) to provide an effective thermal contact between the IC and the PCB. The PowerPAD™ package (thermally enhanced HTSSOP) combines fine-pitch, surface-mount technology with thermal performance comparable to much larger power packages.
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TAS5112A www.ti.com SLES094B - OCTOBER 2003 - REVISED JUNE 2008 Copper Layer − Component Side Solder PowerPAD TAS5112ACDA 5y11 Vias (f 0.3 mm) 4 mm 8 mm Figure 14. Recommended Land Pattern The lower via pad area, slightly larger than the IC pad itself, is exposed with a window in the solder resist on the bottom surface of the board. It is not coated with solder during the board construction to maintain a flat surface. In production, this can be accomplished with a peelable solder mask.
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TAS5112A www.ti.com SLES094B - OCTOBER 2003 - REVISED JUNE 2008 Insulating Front Panel Stereo Amplifier Board Insulating Back Panel Plastic Top PCB (3.65C/W) 56-Pin DCA Package (1.145C/W) ÔÔÔ ÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓÓ ÔÔÔ Wakefield Type 126 Thermal Compound Under Via Pads (3.2°C/W) 1 mm 8-mm y 10-mm y 40-mm Aluminum Bar (0.09°C/W) Wakefield Type 126 Thermal Compound (0.1°C/W) Aluminum Chassis 7.2 in. y 1 in. y 0.1 in. Thick Sides of U-Shaped Chassis Are 1.25 in. High (3.9°C/W) Figure 15.
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TAS5112A www.ti.com SLES094B - OCTOBER 2003 - REVISED JUNE 2008 LAND PATTERN PCB THERMAL RESISTANCE 7 × 13 vias (5 × 10 mm) 2.2°C/W 5 × 11 vias (4 × 8 mm) 3.6°C/W Thermal Pad To make this system work properly, the following design rules must be followed when using the TAS5112A back end: D The relative timing between the PWM_AP/M_x signals and their corresponding VALID_x signal should not be skewed by inserting delays, because this increases the audible amplitude level of the click.
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TAS5112A www.ti.com SLES094B - OCTOBER 2003 - REVISED JUNE 2008 REFERENCES 6. TAS5036A Six-Channel Digital Audio Processor data manual—TI (SLES061) PWM 1. TAS5000 Digital Audio PWM Processor data manual—TI (SLAS270) 7. TAS3103 Digital Audio Processor With 3D Effects data manual—TI (SLES038) 2. True Digital Audio Amplifier TAS5001 Digital Audio PWM Processor data sheet—TI (SLES009) 8.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 30-Jul-2011 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TAS5112ADFDR Package Package Pins Type Drawing SPQ HTSSOP 2000 DFD 56 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 24.4 Pack Materials-Page 1 8.6 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 15.6 1.8 12.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TAS5112ADFDR HTSSOP DFD 56 2000 367.0 367.0 45.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.