Datasheet

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FEATURES

APPLICATIONS

DESCRIPTION

220

100

120

140

160

180

200

5 10

25 30

40 45

PV -SupplyVoltage(BTL)-Vrms

P -OutputPower-W

4 W

6 W

T =75°C,

DigitalGain=2.5dB

8 W

TAS5162

SLES194D – OCTOBER 2006 – REVISED JULY 2007

2 x 210 Watt STEREO DIGITAL AMPLIFIER POWER STAGE

This system only requires a simple passive LC

demodulation filter to deliver high-quality,

• 2 × 160 W at 10% THD+N Into 8- Ω BTL

high-efficiency audio amplification with proven EMI

• 2 × 210 W at 10% THD+N Into 6- Ω BTL

compliance. This device requires two power

supplies, at 12 V for GVDD and VDD, and at 50V for

• 1 × 300 W at 10% THD+N Into 4- Ω PBTL

(1)

PVDD. The TAS5162 does not require power-up

• >110 dB SNR (A-Weighted, TAS5518

sequencing due to internal power-on reset. The

Modulator)

efficiency of this digital amplifier is greater than 90%

• <0.09% THD+N at 1 W

into 6 Ω , which enables the use of smaller power

supplies and heatsinks.

• Two Thermally Enhanced Package Options:

– DKD (36-pin PSOP3)

The TAS5162 has an innovative protection system

integrated on-chip, safeguarding the device against a

– DDV (44-pin HTSSOP)

wide range of fault conditions that could damage the

• High-Efficiency Power Stage (>90%) With

system. These safeguards are short-circuit

80-m Ω Output MOSFETs

protection, overcurrent protection, undervoltage

• Power-On Reset for Protection on Power Up

protection, and overtemperature protection. The

Without Any Power-Supply Sequencing

TAS5162 has a new proprietary current-limiting

circuit that reduces the possibility of device shutdown

• Integrated Self-Protection Circuits Including

during high-level music transients. A new

Undervoltage, Overtemperature, Overload,

programmable overcurrent detector allows the use of

Short Circuit

lower-cost inductors in the demodulation output filter.

• Error Reporting

BTL OUTPUT POWER vs SUPPLY VOLTAGE

• EMI Compliant When Used With

Recommended System Design

• Intelligent Gate Drive

• Mid-Z Ramp Compatible for reduced "pop

noise"

• Mini/Micro Audio System

• DVD Receiver

• Home Theater

The TAS5162 is a high performance, integrated

stereo digital amplifier power stage with an improved

protection system. The TAS5162 is capable of

driving a 6- Ω bridge-tied load (BTL) at up to 210 W

per channel at THD = 10%, low integrated noise at

(1) The DDV package will deliver the stated maximum power

the output, low THD+N performance without clipping,

levels; however, this is dependant on system

and low idle power dissipation.

configuration. The smaller pad area also makes the

A low-cost, high-fidelity audio system can be built

thermal interface to the heatsink more important. For

multichannel systems that require two channels to be

using a TI chipset, comprising a modulator (e.g.,

driven at full power with the DDV package option, it is

TAS5508) and the TAS5162. PurePath Digital™

recommended to design the system so that the two

channels are in two separate devices.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PurePath Digital, PowerPad are trademarks of Texas Instruments.

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (33 pages)

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TM TAS5162 www.ti.com SLES194D – OCTOBER 2006 – REVISED JULY 2007 2 x 210 Watt STEREO DIGITAL AMPLIFIER POWER STAGE • • • • • • • • • • • • • 2×160 W at 10% THD+N Into 8-Ω BTL 2×210 W at 10% THD+N Into 6-Ω BTL 1×300 W at 10% THD+N Into 4-Ω PBTL (1) >110 dB SNR (A-Weighted, TAS5518 Modulator) <0.
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TAS5162 www.ti.com SLES194D – OCTOBER 2006 – REVISED JULY 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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TAS5162 www.ti.
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TAS5162 www.ti.com SLES194D – OCTOBER 2006 – REVISED JULY 2007 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) TAS5162 VDD to AGND –0.3 V to 13.2 V GVDD_X to AGND –0.3 V to 13.2 V PVDD_X to GND_X (2) –0.3 V to 71 V OUT_X to GND_X (2) –0.3 V to 71V BST_X to GND_X (2) –0.3 V to 79.7 V VREG to AGND –0.3 V to 4.2 V GND_X to GND –0.3 V to 0.3 V GND_X to AGND –0.3 V to 0.3 V GND to AGND –0.3 V to 0.3 V PWM_X, OC_ADJ, M1, M2, M3 to AGND –0.
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TAS5162 www.ti.com SLES194D – OCTOBER 2006 – REVISED JULY 2007 Terminal Functions TERMINAL NAME (1) DKD NO. DDV NO. FUNCTION (1) DESCRIPTION AGND 9 11 P Analog ground BST_A 35 43 P HS bootstrap supply (BST), external .033-μF capacitor to OUT_A required BST_B 28 34 P HS bootstrap supply (BST), external .033-μF capacitor to OUT_B required BST_C 27 33 P HS bootstrap supply (BST), external .033-μF capacitor to OUT_C required BST_D 20 24 P HS bootstrap supply (BST), external .
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TAS5162 www.ti.com SLES194D – OCTOBER 2006 – REVISED JULY 2007 SYSTEM BLOCK DIAGRAM VDD 4 Undervoltage Protection OTW Internal Pullup Resistors to VREG SD M1 Protection and I/O Logic M2 M3 4 VREG VREG Power On Reset AGND Temp. Sense GND RESET_AB Overload Protection RESET_CD Isense OC_ADJ GVDD_D BST_D PVDD_D PWM_D PWM Rcv. Ctrl. Timing Gate Drive OUT_D BTL/PBTL−Configuration Pulldown Resistor GND_D GVDD_C BST_C PVDD_C PWM_C PWM Rcv. Ctrl.
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TAS5162 www.ti.
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TAS5162 www.ti.com SLES194D – OCTOBER 2006 – REVISED JULY 2007 RECOMMENDED OPERATING CONDITIONS MIN TYP MAX UNIT PVDD_X Half-bridge supply DC supply voltage 0 50 52.5 V GVDD_X Supply for logic regulators and gate-drive circuitry DC supply voltage 10.8 12 13.2 V VDD Digital regulator input DC supply voltage 10.8 12 13.2 V 4.6 6-8 2.5 3-8 RL (BTL) RL (SE) Output filter: L = 10 μH, C = 470 nF.
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TAS5162 www.ti.com SLES194D – OCTOBER 2006 – REVISED JULY 2007 AUDIO SPECIFICATIONS (Single-Ended Output) (continued) PVDD_X = 50 V, GVDD = VDD = 12 V, SE mode, RL = 3 Ω, ROC = 22 KΩ, audio frequency = 1 kHz, AES17 filter, FPWM = 384 kHz, case temperature = 75°C, unless otherwise noted. Audio performance is recorded as a chipset, using TAS5086 PWM processor with an effective modulation index limit of 96.1%. All performance is in accordance with recommended operating conditions unless otherwise specified.
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TAS5162 www.ti.com SLES194D – OCTOBER 2006 – REVISED JULY 2007 ELECTRICAL CHARACTERISTICS RL= 6 Ω, FPWM = 384 kHz, unless otherwise noted. All performance is in accordance with recommended operating conditions unless otherwise specified. PARAMETER TEST CONDITIONS TAS5162 MIN TYP MAX 2.95 3.3 3.
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TAS5162 www.ti.com SLES194D – OCTOBER 2006 – REVISED JULY 2007 TYPICAL CHARACTERISTICS, BTL CONFIGURATION TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER OUTPUT POWER vs SUPPLY VOLTAGE 5 220 PVDD (4 W) = 38.5 V, TC = 75°C, Digital Gain = 2.5 dB 1 0.5 4W 6W 0.1 0.05 160 140 4W 120 8W 100 80 60 8W 0.02 40 20 0.01 0.005 20m 0 100m 200m 1 2 10 20 100 0 300 5 PO - Output Power (BTL) - W 10 15 20 25 30 35 40 45 PVDD - Supply Voltage (BTL) - Vrms Figure 1. Figure 2.
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TAS5162 www.ti.com SLES194D – OCTOBER 2006 – REVISED JULY 2007 TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued) SYSTEM POWER LOSS vs OUTPUT POWER SYSTEM OUTPUT POWER vs CASE TEMPERATURE 52 240 TC = 75°C, Digital Gain = 2.5 dB, PVDD (4 W) = 38.5 V 48 44 4W 200 PO - Output Power - W 40 Power Loss 36 32 28 24 8W 20 4W 180 8W 160 140 120 100 16 80 60 12 PVDD (4 W) = 38.5 V, Digital Gain = 2.
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TAS5162 www.ti.com SLES194D – OCTOBER 2006 – REVISED JULY 2007 TYPICAL CHARACTERISTICS, SE CONFIGURATION OUTPUT POWER vs SUPPLY VOLTAGE 10 5 110 TC = 75°C, Digital Gain = 2.5 dB 90 1 80 PO - Output Power - W 2 0.5 0.2 TC = 75°C, Digital Gain = 2.5 dB 100 3W 0.1 0.05 4W 3W 70 60 4W 50 40 30 0.02 20 0.01 0.005 20m 10 100m 200m 1 2 10 20 100 0 0 PO - Output Power (SE) - W 5 10 15 20 25 30 35 40 45 PVDD - Supply Voltage (SE) - Vrms Figure 8. 50 Figure 9.
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TAS5162 www.ti.com SLES194D – OCTOBER 2006 – REVISED JULY 2007 TYPICAL CHARACTERISTICS, PBTL CONFIGURATION TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER OUTPUT POWER vs SUPPLY VOLTAGE 5 TC = 75°C, Digital Gain = 2.5 dB 2 PO - Output Power - W THD+N - Total Harmonic Distortion + Noise - % 10 1 0.5 6W 0.2 0.1 0.05 4W 8W 0.02 0.01 0.
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TAS5162 www.ti.com SLES194D – OCTOBER 2006 – REVISED JULY 2007 PVDD 10 Ω GVDD 10 mF 3.3 Ω 100 nF 1000 mF 63 V 10 nF 100 V 10 Ω 10 nF 100 V TAS5162DKD 100 nF 1 Microcontroller 2 0Ω Optional 3 Shutdown 35 5 VALID OTW PVDD_A 22 kΩ 7 PWM2_P 1Ω OUT_A RESET_AB GND_A PWM_B GND_B OC_ADJ 12 13 28 AGND BST_B VREG BST_C 26 M3 PVDD_C M2 OUT_C M1 GND_C PWM_C GND_D RESET_CD OUT_D 10 Ω 100 nF 33 nF 100 nF 100 V 1.0 mF 100 V 100 nF 100 V 1.
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TAS5162 www.ti.com SLES194D – OCTOBER 2006 – REVISED JULY 2007 PVDD 10 Ω GVDD 10 mF 3.3 Ω 100 nF 1000 mF 63 V 10 nF 100 V 10 Ω 10 nF 100 V TAS5162DKD 100 nF 1 Microcontroller 2 0Ω Optional 3 Shutdown 35 5 VALID PVDD_A OUT_A RESET_AB GND_A PWM_B GND_B 1Ω 7 OC_ADJ 12 13 28 AGND BST_B VREG BST_C 16 26 M3 PVDD_C M2 OUT_C M1 GND_C PWM_C GND_D RESET_CD OUT_D 10 Ω 100 nF 100 nF 100 V 1.0 mF 100 V 1.
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TAS5162 www.ti.com SLES194D – OCTOBER 2006 – REVISED JULY 2007 10 Ω 100 nF GVDD 10 mF PVDD 1.0 mF 100 V 10 Ω 3.3 Ω TAS5162DKD 100 nF 1 Microcontroller 2 0Ω Optional 3 Shutdown 36 GVDD_B GVDD_A 35 OTW 5 VALID 33 PWM_A OUT_A RESET_AB GND_A 22 kW PWM3_P 1Ω 7 PWM_B GND_B OC_ADJ OUT_B 29 GND PVDD_B 9 100 nF TAS5508 12 13 BST_B VREG BST_C PVDD_C M2 OUT_C 1.0 mF 100 V 10 nF 100 V 1.
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TAS5162 www.ti.com SLES194D – OCTOBER 2006 – REVISED JULY 2007 10 Ω GVDD PVDD 100 nF 3.3 Ω 10 mF 10 Ω TAS5162DKD 100 nF 1 Microcontroller 2 0Ω Optional 3 Shutdown GVDD_A 35 OTW SD 5 VALID 22 kW 1Ω 7 RESET_AB GND_A PWM_B GND_B OC_ADJ 28 BST_C 26 M3 PVDD_C M2 OUT_C M1 GND_C PWM_C GND_D RESET_CD OUT_D 47 mF 10 Ω 1.0 mF 100 V 1.
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TAS5162 www.ti.com SLES194D – OCTOBER 2006 – REVISED JULY 2007 10 Ω GVDD 10 mF PVDD 100 nF 3.3 Ω 10 Ω 100 nF 1 Microcontroller 2 0Ω Optional 3 Shutdown 36 GVDD_B GVDD_A 35 OTW SD 5 VALID 1Ω 7 33 PWM_A OUT_A RESET_AB GND_A PWM_B GND_B OC_ADJ OUT_B 13 28 AGND BST_B VREG BST_C M3 26 No connect 16 M2 OUT_C M1 GND_C PWM_C GND_D 47 mF 10 Ω 100 nF 100 V 470 nF 63 V 1.0 mF 100 V 1.0 mF 100 V 100 nF 100 V 3.
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TAS5162 www.ti.com SLES194D – OCTOBER 2006 – REVISED JULY 2007 THEORY OF OPERATION POWER SUPPLIES To facilitate system design, the TAS5162 needs only a 12-V supply in addition to the (typical) 50-V power-stage supply. An internal voltage regulator provides suitable voltage levels for the digital and low-voltage analog circuitry. Additionally, all circuitry requiring a floating voltage supply, e.g.
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TAS5162 www.ti.com SLES194D – OCTOBER 2006 – REVISED JULY 2007 Characteristics section of this data sheet). Although not specifically required, it is a good practice to hold RESET_AB and RESET_CD low during power down, thus preventing audible artifacts including pops or clicks. When the TAS5162 is being used with TI PWM modulators such as the TAS5508, no special attention to the state of RESET_AB and RESET_CD is required, provided that the chipset is configured as recommended.
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TAS5162 www.ti.com SLES194D – OCTOBER 2006 – REVISED JULY 2007 Use of TAS5162 Capable Systems in High-Modulation-Index This device requires at least 50 ns of low time on the output per 384-kHz PWM frame rate in order to keep the bootstrap capacitors charged. As an example, if the modulation index is set to 99.2% in the TAS5508, this setting allows PWM pulse durations down to 20 ns.
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TAS5162 www.ti.com SLES194D – OCTOBER 2006 – REVISED JULY 2007 system that asserts an active-low warning signal (OTW) when the device junction temperature exceeds 125°C (nominal) and, if the device junction temperature exceeds 155°C (nominal), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-impedance (Hi-Z) state and SD being asserted low. OTE is latched in this case and RESET_AB and RESET_CD must be asserted low.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com (4) 18-Oct-2013 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) TAS5162DDVR HTSSOP DDV 44 2000 330.0 24.4 TAS5162DKDR HSSOP DKD 36 500 330.0 24.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 8.6 15.6 1.8 12.0 24.0 Q1 14.7 16.4 4.0 20.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TAS5162DDVR HTSSOP DDV 44 2000 367.0 367.0 45.0 TAS5162DKDR HSSOP DKD 36 500 367.0 367.0 45.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.