Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLinear ICsLinear IC - Audio amplifier 1-channel (mono) Class D HSSOP 36

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FEATURES

APPLICATIONS

PVDD Supply Voltage − V

120

150

180

210

240

270

300

330

0 5 10 15 20 25 30 35 40 45 50

= 75°C

THD+N at 10%

− Output Power − W

G001

8 Ω

6 Ω

4 Ω

DESCRIPTION

TAS5261

SLES188 – AUGUST 2006

315-W Mono BTL Digital Amplifier Power Stage

The TAS5261 has complete protection circuitry

• Total Output Power

integrated on chip, safeguarding the device and

– 125 W Into 8 Ω at <0.09% THD+N

speakers against fault conditions that could damage

– 220 W Into 6 Ω at 10% THD+N

the system. These protection features are

short-circuit protection, overcurrent protection,

– 315 W Into 4 Ω at 10% THD+N

undervoltage protection, and a loss of pulse-width

• 110-dB SNR (A-Weighted with TAS5518

modulation (PWM) input signal (PWM Activity

modulator)

Detector).

• Supports Pulse-Width Modulation (PWM)

A power-on reset (POR) circuit is used to eliminate

Frame Rates of 192 kHz to 384 kHz

power-supply sequencing that is normally required

• Resistor-Programmable Current Limit

for most H-bridge designs.

• Integrated Self-Protection Circuit Including:

OUTPUT POWER

– Under Voltage Protection

– Over Temperature Warning and Error

PVDD_x SUPPLY VOLTAGE

– Over Load Protection

– Short Circuit (OC) Protection

– PWM Activity Dectector

• Power-On Reset (POR) to Eliminate System

Power-Supply Sequencing

• Thermally-Enhanced Package DKD (36-pin

PSOP3)

• EMI Compliant When Used With

Recommended System Design

• Error Reporting 3.3-V and 5-V Compliant

• AV Receivers

• DVD Receivers

• Mini/Micro Component Systems

• Home Theater Systems

The TAS5261 is a high-performance, integrated

mono digital amplifier power stage designed to drive

4- Ω to 8- Ω speakers with low harmonic distortion.

This system requires only a simple, passive

demodulation filter to deliver high-quality,

high-efficiency audio amplification.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (26 pages)

PAGE 1
TM TAS5261 www.ti.com SLES188 – AUGUST 2006 315-W Mono BTL Digital Amplifier Power Stage FEATURES • • • • • • • • Total Output Power – 125 W Into 8 Ω at <0.
PAGE 2
TAS5261 www.ti.com SLES188 – AUGUST 2006 DEVICE INFORMATION The TAS5261 is available in a thermally-enhanced 36-pin PSOP3 PowerPAD™ package. The heat slug is located on the top side of the device for convenient thermal coupling to a heat sink.
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TAS5261 www.ti.com SLES188 – AUGUST 2006 DISSIPATION RATINGS PARAMETER CONDITION TYPICAL (DKD) RθJC BTL channel (four transistors) 0.6°C/W RθJC One transistor 2.38°C/W 80 mm2 Pad area Protection Mode Protection modes are selected by shorting M1, M2, and M3 to VREG or GND. Table 1.
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TAS5261 www.ti.com SLES188 – AUGUST 2006 TERMINAL FUNCTIONS TERMINAL DESCRIPTION PIN NO. AGND 9 I Analog ground BST_A 1 P Bootstrap, A side BST_B 18 I Bootstrap, B side GND 8, 16 I Power ground GVDD_A 2 P Gate-drive voltage supply, A side GVDD_B 17 I Gate-drive voltage supply, B side M1 13 I Mode-selection 1 (LSB) M2 12 I Mode-selection 2 (MSB) M3 11 I Reserved OC_ADJ 7 I Overcurrent threshold programming OTW 3 O Overtemperature warning. Open drain, active low.
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TAS5261 www.ti.
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TAS5261 www.ti.com SLES188 – AUGUST 2006 OTW M1 M2 M3 PROTECTION & I/O LOGIC SD VDD POWER-UP RESET UVP VREG VREG AGND TEMP SENSE GVDD_A GVDD_B GND OVER-LOAD PROT . CURRENT SENSE CB3C OC_ADJ RESET GVDD _B PWM ACTIVITY DETECTOR BST_B PVDD_B (x3) PWM_B PWM RECEIVER CONTROL TIMING CONTROL GATE-DRIVE OUT_B (x3) PGND (x3) GVDD _A BST_A PVDD_A (x3) PWM_A PWM RECEIVER CONTROL TIMING CONTROL GATE-DRIVE OUT_A (x3) PGND (x3) Figure 2.
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TAS5261 www.ti.com SLES188 – AUGUST 2006 ORDERING INFORMATION TA PACKAGE DESCRIPTION 0°C to 70°C TAS5261DKD 36-pin PSOP3 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VDD to AGND –0.3 13.2 V GVDD_x to AGND –0.3 13.2 V PVDD_x to PGND_x (2) –0.3 71 V OUT_x to PGND_x (2) –0.3 71 V BST_x to PGND_x (2) –0.3 79.7 V GVDD_x (2) BST_x to –0.3 66.5 V VREG to AGND –0.3 4.2 V PGND_x to GND –0.3 0.
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TAS5261 www.ti.com SLES188 – AUGUST 2006 RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT 0 50 52.5 V Gate-drive power supply 10.8 (1) 12 13.2 V VDD Digital regulator supply voltage 10.8 (1) 12 13.
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TAS5261 www.ti.com SLES188 – AUGUST 2006 ELECTRICAL CHARACTERISTICS Audio frequency = 1 kHz, PVDD_x = 50 V, GVDDx = 12 V, VDD = 12 V, RL = 8 Ω , fs = 384 kHz, OC_ADJ = 22 kΩ, TC = 75°C, output filter is LDEM = 10 µH, CL = 1 µF (unless otherwise noted). AC performance is recorded as a chipset, TAS5518 as front end with an effective modulation index of 96.1% and TAS5261 as the power stage. PCB and system configuration are in accordance with recommended design guidelines.
PAGE 10
TAS5261 www.ti.com SLES188 – AUGUST 2006 ELECTRICAL CHARACTERISTICS GVDD_x = 12 V ± 10%, VDD = 12 V ± 10%, TJ = 25°C (unless otherwise noted) PARAMETER CONDITIONS MIN TYP MAX UNIT Logic-Level and Open-Drain Outputs VIH High-level input voltage Static VIL Low-level input voltage Static Ilkg (1) Input leakage current 0.
PAGE 11
TAS5261 www.ti.com SLES188 – AUGUST 2006 TYPICAL CHARACTERISTICS blk TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER 10 5 2 1 0.5 T H D + N % 0.2 0.1 0.05 0.02 0.01 80m 200m 500m 1 2 5 10 20 50 100 200 300 Output Power W Red - 4 Ohm Blue - 6 Ohm Magenta - 8 Ohm Figure 3.
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TAS5261 www.ti.com SLES188 – AUGUST 2006 TYPICAL CHARACTERISTICS (continued) blk SYSTEM EFFICIENCY vs OUTPUT POWER SYSTEM POWER LOSS vs OUTPUT POWER 100 12 TC = 25°C 11 10 80 8 Power Loss − W Efficiency − % 9 60 40 7 6 5 4 3 20 2 TC = 25°C Two Channels 1 0 0 0 20 40 60 80 100 120 PO − Output Power − W 0 25 50 G004 Figure 6. Figure 7.
PAGE 13
TAS5261 www.ti.com SLES188 – AUGUST 2006 TYPICAL CHARACTERISTICS (continued) blk NOISE AMPLITUDE vs FREQUENCY +0 -5 -10 -15 -20 -25 -30 -35 -40 N o i s e -45 -50 -55 -60 A m p l i t u d e -65 -70 -75 -80 -85 -90 - -95 d B r -100 -105 -110 -115 -120 -125 -130 -135 -140 -145 -150 0 1k 2k 3k 4k 5k 6k 7k 8k 9k 10k 11k 12k 13k 14k 15k 16k 17k 18k 19k 20k 21k 22k f - Frequency - kHz Figure 9.
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TAS5261 www.ti.
PAGE 15
TAS5261 www.ti.com SLES188 – AUGUST 2006 APPLICATION INFORMATION (continued) Recommended Printed Circuit Board (PCB) Layout PCB Requirements • • 2-oz copper (FR-4) recommended PVDD voltage and capacitor selection in accordance with the data sheet Figure 10. PCB (Top Layer) Figure 11.
PAGE 16
TAS5261 www.ti.com SLES188 – AUGUST 2006 THEORY OF OPERATION Power Supplies To facilitate system design, the TAS5261 needs only a 12-V supply in addition to a typical 50-V power-stage supply. An internal voltage regulator provides suitable voltage levels for the digital and low-voltage analog circuitry. Additionally, all circuitry requiring a floating voltage supply, e.g., the high-side gate drive, is accommodated by built-in bootstrap circuitry requiring only a few external capacitors.
PAGE 17
TAS5261 www.ti.com SLES188 – AUGUST 2006 Error Reporting The SD and OTW pins are both active-low, open-drain outputs. Their function is for protection-mode signaling to a PWM controller or other system-control device. Any fault resulting in device shutdown is signaled by the SD pin going low. Likewise, OTW goes low when the device junction temperature exceeds 115°C. (see Table 2). Table 2.
PAGE 18
TAS5261 www.ti.com SLES188 – AUGUST 2006 For added flexibility, the OC threshold is programmable within a limited range using a single external resistor connected between the OC_ADJ pin and AGND. It should be noted that a properly functioning overcurrent detector assumes the presence of a properly designed demodulation filter at the power-stage output. Short-circuit protection is not provided directly at the output pins of the power stage but only on the speaker terminals (after the demodulation filter).
PAGE 19
PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 21
PACKAGE MATERIALS INFORMATION www.ti.com 4-Jun-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device TAS5261DKDR Package Package Pins Type Drawing SPQ HSSOP 500 DKD 36 Reel Reel Diameter Width (mm) W1 (mm) 330.0 24.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 14.7 16.4 4.0 20.0 24.
PAGE 22
PACKAGE MATERIALS INFORMATION www.ti.com 4-Jun-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TAS5261DKDR HSSOP DKD 36 500 337.0 343.0 41.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.