Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLinear ICsLinear IC - Audio amplifier 1-channel (mono) or 2-channel (stereo) Class D HTSSOP 44

FEATURES

DESCRIPTION

APPLICATIONS

150

100

110

120

130

140

0 342

6 8 10 12 14 16 18 20 22 24 26 28 30 32

T =75°C

THD+Nat10%

Ω

P – OutputPower – W

PVDD – SupplyVoltage – V

TAS5352

SLES204A – SEPTEMBER 2007 – REVISED OCTOBER 2007

www.ti.com

125 W STEREO DIGITAL AMPLIFIER POWER STAGE

• Total Power Output (Bridge Tied Load)

– 2 × 125 W at 10% THD+N Into 4 Ω

The TAS5352 is a high-performance, integrated

stereo digital amplifier power stage designed to drive

– 2 × 100 W at 10% THD+N Into 6 Ω

a 4- Ω bridge-tied load (BTL) at up to 125 W per

• Total Power Output (Single Ended)

channel with low harmonic distortion, low integrated

– 4 × 45 W at 10% THD+N Into 3 Ω

noise, and low idle current.

– 4 × 35 W at 10% THD+N Into 4 Ω

The TAS5352 has a complete protection system

• Total Power Output (Parallel Mode)

integrated on-chip, safeguarding the device against a

wide range of fault conditions that could damage the

– 1 × 250 W at 10% THD+N Into 2 Ω

system. These protection features are short-circuit

– 1 × 195 W at 10% THD+N Into 3 Ω

protection, over-current protection, under voltage

• >110 dB SNR (A-Weighted With TAS5518

protection, over temperature protection, and a loss of

Modulator) PWM signal (PWM activity detector).

• <0.1% THD+N (1 W, 1 kHz)

A power-on-reset (POR) circuit is used to eliminate

power-supply sequencing that is required for most

• Supports PWM Frame Rates of 192 kHz to

power-stage designs.

432 kHz

BTL OUTPUT POWER

• Resistor-Programmable Current Limit

• Integrated Self-Protection Circuitry, Including:

SUPPLY VOLTAGE

– Under Voltage Protection

– Overtemperature Warning and Error

– Overload Protection

– Short-Circuit Protection

– PWM Activity Detector

• Standalone Protection Recovery

• Power-On Reset (POR) to Eliminate System

Power-Supply Sequencing

• High-Efficiency Power Stage (>90%) With

80-m Ω Output MOSFETs

• Thermally Enhanced 44-Pin HTSSOP Package

(DDV)

• Error Reporting, 3.3-V and 5.0-V Compliant

• EMI Compliant When Used With

Recommended System Design

• Mini/Micro Audio System

PurePath Digital™

• DVD Receiver

• Home Theater

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2 PurePath Digital, PowerPad are trademarks of Texas Instruments.

3 All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (28 pages)

PAGE 1
TM TAS5352 www.ti.com SLES204A – SEPTEMBER 2007 – REVISED OCTOBER 2007 125 W STEREO DIGITAL AMPLIFIER POWER STAGE FEATURES 1 DESCRIPTION The TAS5352 is a high-performance, integrated stereo digital amplifier power stage designed to drive a 4-Ω bridge-tied load (BTL) at up to 125 W per channel with low harmonic distortion, low integrated noise, and low idle current.
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TAS5352 www.ti.com SLES204A – SEPTEMBER 2007 – REVISED OCTOBER 2007 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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TAS5352 www.ti.com SLES204A – SEPTEMBER 2007 – REVISED OCTOBER 2007 Protection MODE Selection Pins Protection modes are selected by shorting M1, M2, and M3 to VREG or GND.
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TAS5352 www.ti.com SLES204A – SEPTEMBER 2007 – REVISED OCTOBER 2007 ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) TAS5352 VDD to AGND –0.3 V to 13.2 V GVDD_X to AGND –0.3 V to 13.2 V (2) PVDD_X to GND_X –0.3 V to 53 V OUT_X to GND_X (2) –0.3 V to 53 V BST_X to GND_X (2) –0.3 V to 66.2 V BST_X to GVDD_X (2) –0.3 V to 53 V VREG to AGND –0.3 V to 4.2 V GND_X to GND –0.3 V to 0.3 V GND_X to AGND –0.3 V to 0.3 V GND to AGND –0.3 V to 0.
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TAS5352 www.ti.com SLES204A – SEPTEMBER 2007 – REVISED OCTOBER 2007 Terminal Functions TERMINAL NAME DDV NO.
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TAS5352 www.ti.com SLES204A – SEPTEMBER 2007 – REVISED OCTOBER 2007 TYPICAL SYSTEM BLOCK DIAGRAM OTW System Microcontroller SD SD TAS5518 OTW I2C BST_A BST_B RESET_AB RESET_CD VALID PWM_A LeftChannel Output OUT_A Output H-Bridge 1 Input H-Bridge 1 PWM_B OUT_B Bootstrap Capacitors 2nd-Order L-C Output Filter for Each Half-Bridge 2-Channel H-Bridge BTL Mode OUT_C PWM_C 4 34.
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TAS5352 www.ti.com SLES204A – SEPTEMBER 2007 – REVISED OCTOBER 2007 FUNCTIONAL BLOCK DIAGRAM VDD 4 Undervoltage Protection OTW Internal Pullup Resistors to VREG SD M1 Protection and I/O Logic M2 M3 4 VREG VREG Power On Reset AGND Temp. Sense GND RESET_AB Overload Protection RESET_CD OC_ADJ Isense GVDD_D BST_D PVDD_D PWM_D PWM Rcv. Ctrl. Timing Gate Drive OUT_D BTL/PBTL−Configuration Pulldown Resistor GND_D GVDD_C BST_C PVDD_C PWM_C PWM Rcv. Ctrl.
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TAS5352 www.ti.com SLES204A – SEPTEMBER 2007 – REVISED OCTOBER 2007 RECOMMENDED OPERATING CONDITIONS MIN TYP MAX UNIT PVDD_X Half-bridge supply voltage 0 34.5 37 V GVDD_X Supply voltage for logic regulators and gate-drive circuitry 10.8 12 13.2 V VDD Digital regulator supply voltage 10.8 12 13.2 V 3 4 2.25 3 RL (BTL) RL (SE) RL (PBTL) Resistive load impedance (no Cycle-by_Cycle current control), recommended demodulation filter 1.
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TAS5352 www.ti.com SLES204A – SEPTEMBER 2007 – REVISED OCTOBER 2007 AUDIO SPECIFICATIONS (Single-Ended Output) Audio performance is recorded as a chipset consisting of a TAS5086 pwm processor (modulation index limited to 97.7%) and a TAS5352 power stage. PCB and system configuraton are in accordance with recommended guidelines. Audio frequency = 1kHz, PVDD_x = 34.5 V, GVDD_x = 12 V, RL = 4Ω, fS = 384 kHz, ROC = 22 kΩ, TC = 75°C, Output Filter: LDEM = 20 μH, CDEM = 1.0 μF, unless otherwise noted.
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TAS5352 www.ti.com SLES204A – SEPTEMBER 2007 – REVISED OCTOBER 2007 ELECTRICAL CHARACTERISTICS PVDD_x = 34.5 V, GVDD_X = 12 V, VDD = 12 V, TC (Case temperature) = 75°C, fS = 384 kHz, unless otherwise specified. PARAMETER TAS5352 TEST CONDITIONS MIN TYP MAX 3 3.3 3.6 Operating, 50% duty cycle 7.2 17 Idle, reset mode 5.
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TAS5352 www.ti.com SLES204A – SEPTEMBER 2007 – REVISED OCTOBER 2007 ELECTRICAL CHARACTERISTICS (continued) PVDD_x = 34.5 V, GVDD_X = 12 V, VDD = 12 V, TC (Case temperature) = 75°C, fS = 384 kHz, unless otherwise specified.
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TAS5352 www.ti.
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TAS5352 www.ti.com SLES204A – SEPTEMBER 2007 – REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS, SE CONFIGURATION TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER OUTPUT POWER vs SUPPLY VOLTAGE 5 TC = 75°C THD+N at 10% 2 PO – Output Power – W THD+N – Total Hamonic Distortion – % 10 1 0.5 0.2 3Ω 0.1 0.05 4Ω 0.02 0.01 0.005 20m 50m 100m 200m 500m 1 5 2 10 20 60 57.5 55 52.5 50 47.5 45 42.5 40 37.5 35 32.5 30 27.5 25 22.5 20 17.5 15 12.5 10 7.5 5 2.
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TAS5352 www.ti.com SLES204A – SEPTEMBER 2007 – REVISED OCTOBER 2007 TYPICAL CHARACTERISTICS, PBTL CONFIGURATION TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER OUTPUT POWER vs SUPPLY VOLTAGE 300 5 TC = 75°C THD+N at 10% TC = 75°C THD+N at 10% 280 4Ω 260 240 2 220 PO – Output Power – W THD+N – Total Hamonic Distortion – % 10 1 0.5 2Ω 0.2 0.1 0.05 3Ω 4Ω 2 200 180 160 3Ω 4 140 120 4Ω 100 80 60 0.02 40 8Ω 0.01 0.
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TAS5352 www.ti.com SLES204A – SEPTEMBER 2007 – REVISED OCTOBER 2007 APPLICATION INFORMATION PCB Material Recommendation FR-4 Glass Epoxy material with 2 oz. (70 μm) is recommended for use with the TAS5352. The use of this material can provide for higher power output, improved thermal performance, and better EMI margin (due to lower PCB trace inductance. PVDD Capacitor Recommendation The large capacitors used in conjunction with each full-birdge, are referred to as the PVDD Capacitors.
PAGE 16
TAS5352 www.ti.com SLES204A – SEPTEMBER 2007 – REVISED OCTOBER 2007 GVDD (+12 V) PVDD 10 Ω 10 Ω 3.3 Ω 470 µF 50 V 100 nF 100 nF 10 nF 50 V TAS5352DDV GND GND GVDD_B Microcontroller OTW I2C GND PWM1_P VALID 22 k NC NC PVDD_A SD PVDD_A PWM_A OUT_A RESET_AB GND_A PWM_B GND_B OC_ADJ OUT_B AGND VREG 100 nF PWM2_P TAS5508/18 0Ω OUT_C M1 GND_C PWM_C GND_D GND 10 nF 50 V 100 nF 50 V GND 1 nF 50 V GND 10 nF 50 V 3.3 Ω 10 µH 10 µH 33 nF 25V PVDD_D NC PVDD_D GND NC 3.
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TAS5352 www.ti.com SLES204A – SEPTEMBER 2007 – REVISED OCTOBER 2007 GVDD (+12 V) PVDD 10 Ω 10 Ω 3.
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TAS5352 www.ti.com SLES204A – SEPTEMBER 2007 – REVISED OCTOBER 2007 GVDD (+12 V) PVDD 10 Ω 10 Ω 3.
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TAS5352 www.ti.com SLES204A – SEPTEMBER 2007 – REVISED OCTOBER 2007 THEORY OF OPERATION POWER SUPPLIES To facilitate system design, the TAS5352 needs only a 12 V supply in addition to the (typical) 34.5 V power-stage supply. An internal voltage regulator provides suitable voltage levels for the digital and low-voltage analog circuitry. Additionally, all circuitry requiring a floating voltage supply, e.g.
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TAS5352 www.ti.com SLES204A – SEPTEMBER 2007 – REVISED OCTOBER 2007 Characteristics section of this data sheet). Although not specifically required, it is a good practice to hold RESET_AB and RESET_CD low during power down, thus preventing audible artifacts including pops or clicks. signal using the system microcontroller and responding to an overtemperature warning signal by, e.g., turning down the volume to prevent further heating of the device resulting in device shutdown (OTE).
PAGE 21
TAS5352 www.ti.com SLES204A – SEPTEMBER 2007 – REVISED OCTOBER 2007 voltage on the bootstrap capacitors is less than required for proper control of the High-Side MOSFETs, the device will initiate bootstrap capacitor recharge sequences until the bootstrap capacitors are properly charged for robust operation. This function may be activated with PWM pulses less than 30 nS. Therefore, TI strongly recommends using a TI PWM processor, such as TAS5518, TAS5086 or TAS5508, with the modulation index set at 97.
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TAS5352 www.ti.com SLES204A – SEPTEMBER 2007 – REVISED OCTOBER 2007 Overtemperature Protection DEVICE RESET The TAS5352 has a two-level temperature-protection system that asserts an active-low warning signal (OTW) when the device junction temperature exceeds 125°C (typical) and, if the device junction temperature exceeds 155°C (typical), the device is put into thermal shutdown, resulting in all half-bridge outputs being set in the high-impedance (Hi-Z) state and SD being asserted low.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TAS5352DDVR Package Package Pins Type Drawing SPQ HTSSOP 2000 DDV 44 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 24.4 Pack Materials-Page 1 8.6 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 15.6 1.8 12.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TAS5352DDVR HTSSOP DDV 44 2000 367.0 367.0 45.
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