TAS5548 8-Channel HD Compatible Audio Processor with ASRC and PWM Output Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
TAS5548 www.ti.com SLES270 – NOVEMBER 2012 8-Channel HD Compatible Audio Processor with ASRC and PWM Output Check for Samples: TAS5548 1 Introduction 1.
TAS5548 www.ti.com 1.2 SLES270 – NOVEMBER 2012 Overview Serial Audio Receiver 2x Stereo Serial Audio Receiver 2x Stereo Serial Audio Transciever Stereo Fixed Flow Digital Audio Processor (DAP) 4ch ASRC Bypass 10 ch input 8ch Processor 8ch Output Mixer 4ch ASRC Clocks (Osc, PLL etc) 12.288 Energy Manager (EMO) Power Supply Volume Control (PSVC) 8ch PWM Generator + Headphone (PWM) I2C Control MCU Power Figure 1-1.
TAS5548 SLES270 – NOVEMBER 2012 www.ti.com 2 Description 2.1 Physical Characteristics 2.1.
TAS5548 www.ti.com 2.1.2 SLES270 – NOVEMBER 2012 Terminal Descriptions TERMINAL NAME NO. TYPE (1) 5-V TOLERANT TERMINATION (2) DESCRIPTION AVDD_PWM 50 P 3.3-V analog power supply for PWM. This terminal can be connected to the same power source used to drive power terminal DVDD; but to achieve low PLL jitter, this terminal should be bypassed to AVSS_PWM with a 0.1-μF low-ESR capacitor. AVSS 5 P Analog ground AVSS_PWM 51 P Analog ground for PWM.
TAS5548 SLES270 – NOVEMBER 2012 TERMINAL NAME NO. www.ti.com TYPE (1) 5-V TOLERANT TERMINATION (2) DESCRIPTION Pullup System reset input, active-low. A system reset is generated by applying a logic low to this terminal. RESET is an asynchronous control signal that restores the TAS5548 to its default conditions, sets the valid output low, and places the PWM in the hard-mute state (Non PWM Switching). Master volume is immediately set to full attenuation.
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TAS5548 SLES270 – NOVEMBER 2012 2.4 www.ti.com TAS5548 Functional Description Figure 1-1 shows the TAS5548 functional structure. The following sections describe the TAS5548 functional blocks: • Power Supply • Clock, PLL, and Serial Data Interface • Serial Control Interface • Device Control • Digital Audio Processor • PWM Section • 8 Channel ASRC 2.4.1 Power Supply The power-supply section contains 1.
TAS5548 www.ti.com SLES270 – NOVEMBER 2012 Table 2-1. Serial Data Formats (continued) RECEIVE SERIAL DATA FORMAT WORD LENGTH Right-justified 20 Right-justified 24 I2S 16 I2S 20 2 I S 24 Left-justified 16 Left-justified 20 Left-justified 24 Serial data is input on SDIN1-5. The device will accept 32, 44.1, 48, 88.2, 96, 176.
TAS5548 SLES270 – NOVEMBER 2012 2.4.7.1 www.ti.com TAS5548 Audio-Processing Configurations The 32-kHz to 96-kHz configuration supports eight channels of data processing that can be configured either as eight channels, or as six channels with two channels for separate stereo line outputs. All data is SRC'd to 96kHz in this mode, and processed in the DAP at 96kHz. The 176.
TAS5548 www.ti.com 2.4.7.2 SLES270 – NOVEMBER 2012 TAS5548 Audio-Processing Feature Sets The audio processing architecture of the TAS5548 DAP for normal and double speed configurations is shown below. Table 2-2. TAS5548 Audio-Processing Feature Sets FEATURE 32 kHz–96 kHz 8-CHANNEL FEATURE SET Signal-processing channels Master volume 176.
TAS5548 SLES270 – NOVEMBER 2012 2.4.8 www.ti.com Pulse Width Modulation Schemes TAS5548 supports three PWM modulations schemes: AD Mode, BD Mode and Ternary Mode. Ternary mode is selected using register 0X25, bit D5. For AD and BD Modulation schemes, this bit should be set to 0. AD/BD mode is selected via input mux registers 0X30-0X33. Following PWM timing diagram shows the three different schemes. PWM+ PWM+V Differential voltage -V Figure 2-2.
TAS5548 www.ti.com SLES270 – NOVEMBER 2012 (Center of Positive Signal) PWM+ Idle PWM- PWM+ >0 PWMoffset PWM + <0 PWM - Center of Negative Signal) Figure 2-4.
TAS5548 SLES270 – NOVEMBER 2012 www.ti.com 3 TAS5548 DAP Architecture 3.1 TAS5548 DAP Architecture Diagrams The TAS5548 defaults to processing audio data (post ASRC) at double rate. In the TAS5548, this is set to 96kHz (by the external XTAL used). . Additional support is provided for native 192kHz support. 4ch of audio processing is available in 192kHz native processing mode. Figure 3-1 shows the TAS5548 DAP architecture for fS ≤ 96 kHz.
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TAS5548 SLES270 – NOVEMBER 2012 3.2 www.ti.com I 2C Coefficient Number Formats The architecture of the TAS5548 is contained in ROM resources within the device and cannot be altered. However, mixer gain, level offset, and filter tap coefficients, which can be entered via the I2C bus interface, provide a user with the flexibility to set the TAS5548 to a configuration that achieves system-level goals. The firmware is executed in a 32-bit, signed, fixed-point arithmetic machine.
TAS5548 www.ti.com 3.2.1 SLES270 – NOVEMBER 2012 Digital Audio Processor (DAP) Arithmetic Unit The digital audio processor (DAP) arithmetic unit is a fixed-point computational engine consisting of an arithmetic unit and data and coefficient memory blocks. The DAP arithmetic unit is used to implement all firmware functions - loudness compensation, bass and treble processing, dynamic range control, channel filtering, input and output mixing.
TAS5548 SLES270 – NOVEMBER 2012 www.ti.com 8-Bit ALU Operation (Without Saturation) Rollover 10110111 (-73) + 11001101 (-51) 10000100 (-124) + 11010011 (-45) -73 -51 -124 + -45 01010111 (57) + 00111011 (59) 10010010 (-110) + + -169 59 -110 Figure 3-6.
TAS5548 www.ti.com 3.2.2 SLES270 – NOVEMBER 2012 28-Bit 5.23 Number Format All mixer gain coefficients are 28-bit coefficients using a 5.23 number format. Numbers formatted as 5.23 numbers have 5 bits to the left of the binary point and 23 bits to the right of the binary point. This is shown in Figure 3-7. 2−23 Bit 2−4 Bit 2−1 Bit 20 Bit 23 Bit Sign Bit S_xxxx.xxxx_xxxx_xxxx_xxxx_xxxx_xxx M0007-01 Figure 3-7. 5.23 Format The decimal value of a 5.
TAS5548 SLES270 – NOVEMBER 2012 www.ti.com As Figure 3-9 shows, the hexadecimal (hex) value of the integer part of the gain coefficient cannot be concatenated with the hex value of the fractional part of the gain coefficient to form the 32-bit I2C coefficient. The reason is that the 28-bit coefficient contains 5 bits of integer, and thus the integer part of the coefficient occupies all of one hex digit and the most significant bit of the second hex digit.
TAS5548 www.ti.com SLES270 – NOVEMBER 2012 Gain Coefficient 28 32 SDIN1-L Gain Coefficient 60 28 60 32 SUM SDIN1-R Gain Coefficient 60 28 32 SDIN4-R M0011-01 Figure 3-11. Input Crossbar Mixer 3.4 Biquad Filters For 32-kHz to 96-kHz data, the TAS5548 provides 56 biquads across the eight channels (seven per channel). For 176.4-kHz and 192-kHz data, the TAS5548 has 32 biquads across the three channels (seven per channel).
TAS5548 SLES270 – NOVEMBER 2012 www.ti.com All five coefficients for one biquad filter structure are written to one I2C register containing 20 bytes (or five 32-bit words). The structure is the same for all biquads in the TAS5548. Registers 0x51–0x88 show all the biquads in the TAS5548. Note that u[31:28] bits are unused and default to 0x0. Table 3-1. Contents of One 20-Byte Biquad Filter Register (Default = All-Pass) 3.
TAS5548 www.ti.com SLES270 – NOVEMBER 2012 For post-SRC 192-kHz data, the TAS5548 has two bass and treble tone controls. Each control has a ±18dB I2C control range with selectable corner frequencies and second-order slopes. These controls operate two channel groups: • L, R and C • Sub – Sub only has bass and no treble. The bass and treble filters use a soft update rate that does not produce artifacts during adjustment. Table 3-2.
TAS5548 SLES270 – NOVEMBER 2012 www.ti.com V Audio In Audio Out Loudness Biquad H(z) Loudness Function = f(V) V B0017-01 Figure 3-13. Loudness Compensation Functional Block Diagram Loudness function = f(V) = G × [2(Log V) × LG + LO] + O or alternatively, Loudness function = f(V) = G × [VLG × 2LO] + O For example, for the default values LG = –0.5, LO = 0, G = 1, and O = 0, then: Loudness function = 1/SQRT(V), which is the recommended transfer function for loudness.
TAS5548 www.ti.com SLES270 – NOVEMBER 2012 Table 3-4. Example Loudness Function Parameters DATA FORMAT I2C SUBADDRESS Controls shape of loudness curves 5.23 Loudness gain Loudness function LO Loudness offset G Gain O Offset LOUDNESS TERM DESCRIPTION H(Z) Loudness biquad LG USAGE EXAMPLE HEX FLOAT 0x95 b0 = 0000 8ACE b1 = 0000 0000 b2 = FFFF 7532 a1 = FF01 1951 a2 = 007E E914 b0 = 0.004236 b1 = 0 b2 = –0.004236 a1 = –1.991415 a2 = 0.991488 5.23 0x91 FFC0 0000 –0.
TAS5548 SLES270 – NOVEMBER 2012 www.ti.com All of the TAS5548 default values for DRC can be used except for the DRC1 decay and DRC2 decay. Table 3-5 shows the recommended time constants and their hex values. If the user wants to implement other DRC functions, Texas Instruments recommends using the GUI available from Texas Instruments. The tool allows the user to select the DRC transfer function graphically. It then outputs the TAS5548 hex coefficients for download to the TAS5548. Table 3-5.
TAS5548 www.ti.com SLES270 – NOVEMBER 2012 Figure 3-16 illustrates a typical DRC transfer function. DRC − Compensated Output Region 0 Region 1 Region 2 k2 k1 1:1 Transfer Function Implemented Transfer Function k0 O2 O1 T1 T2 DRC Input Level M0014-01 Figure 3-16. Dynamic Range Compression (DRC) Transfer Function Structure The three regions shown in Figure 3-16 are defined by three sets of programmable coefficients: • Thresholds T1 and T2 define region boundaries.
TAS5548 SLES270 – NOVEMBER 2012 • RMS estimator—This DRC element derives an estimate of the rms value of the audio data stream into the DRC. For the DRC block shared by Ch1 and Ch2, two estimates are computed—an estimate of the Ch1 audio data stream into the DRC, and an estimate of the Ch2 audio data stream into the DRC. The outputs of the two estimators are then compared, sample-by-sample, and the larger-valued sample is forwarded to the compression/expansion coefficient computation engine.
TAS5548 www.ti.com SLES270 – NOVEMBER 2012 T1 and T2 are the threshold settings in dB, k1 is the slope for region 1, and O2 is the offset in dB at T2. If the user chooses to select a value of O1 that does not obey the above equation, a discontinuity at T1 is realized. Decreasing in volume from T2, the slope k1 remains in effect until the input level T1 is reached.
TAS5548 SLES270 – NOVEMBER 2012 www.ti.com For n : 1 compression, the slope k can be found by: k+1 n*1 In both expansion (1 : n) and compression (n : 1), n is implied to be greater than 1. Thus, for expansion: k = n – 1 means k > 0 for n > 1. Likewise, for compression, appears that k must always lie in the range k > –1. k+1 n*1 means –1 < k < 0 for n > 1. Thus, it The DRC imposes no such restriction and k can be programmed to values as negative as –15.999.
TAS5548 www.ti.com SLES270 – NOVEMBER 2012 – -12 +3 +27(clip) -9 3.10 Downmix Algorithm and I2S Out LEFT CH COEF 0XE3 SDIN1 COEF 0XE7 RIGHT CH SDIN4 CENTER CH RIGHT OUT DOLBY DOWN MIX COEF 0XE4 COEF 0XE5 LS CH LEFT OUT COEF 0XE6 SDIN2 COEF 0XE8 RS CH Figure 3-17. Dolby Downmix The TAS5548 has an excellent feature that can mix the input signals to create a downmix to make the I2S serial output which has an SRC that keeps output sample rate at 48KHz irrespective of input sample rate.
TAS5548 SLES270 – NOVEMBER 2012 www.ti.com 3.11 Stereo Downmixes/(or Fold-Downs) 3.11.1 Left Total/Right Total (Lt/Rt) Lt/Rt is a downmix suitable for decoding with a Dolby Pro Logic upmixer to obtain 5.1 channels again. Lt/Rt is also suitable for stereophonic sound playback on a hi-fi or on headphones. Lt = L + -3dB ´ C + -3dB ´ (-Ls - Rs ) Rt = R + -3dB ´ C + -3dB ´ (Ls + Rs ) where Ls and Rs are phase shifted 90° (5) 3.11.
TAS5548 www.ti.com SLES270 – NOVEMBER 2012 Gain Coefficient 28 Select Output N 32 Gain Coefficient 32 28 Select Output N 32 32 Output 1, 2, 3, 4, 5, or 6 Output 7 or 8 Gain Coefficient 28 Select Output N 32 Gain Coefficient 32 28 Select Output N 32 32 Gain Coefficient 32 28 Select Output N 32 M0011-05 Figure 3-18.
TAS5548 SLES270 – NOVEMBER 2012 4 PWM 4.1 PWM Features www.ti.com The TAS5548 has eight channels of high-performance digital PWM modulators that are designed to drive switching output stages (back ends) in both single-ended (SE) and bridge-tied-load (BTL) configurations. The device uses noise-shaping and sophisticated, error-correction algorithms to achieve high power efficiency and high-performance digital audio reproduction.
TAS5548 www.ti.com 5 SLES270 – NOVEMBER 2012 TAS5548 Controls and Status The TAS5548 provides control and status information from both the I2C registers and device pins. This section describes some of these controls and status functions. The I2C summary and detailed register descriptions are contained in Section 10 and Section 11. 5.1 I2C Status Registers The TAS5548 has two status registers that provide general device information.
TAS5548 SLES270 – NOVEMBER 2012 www.ti.com Because RESET is an asynchronous signal, clicks and pops produced during the application (the leading edge) of RESET cannot be avoided. However, the transition from the hard-mute state (Non PWM Switching) to the operational state is performed using a quiet start-up sequence to minimize noise. This control uses the PWM reset and unmute sequence to shut down and start up the PWM.
TAS5548 www.ti.com SLES270 – NOVEMBER 2012 After the initialization time, the TAS5548 starts the transition to the operational state with the master volume set at mute. Because the TAS5548 has an internal oscillator time base, following the release of reset, oscillator trim command is needed so the TAS5548 can detect the MCLK and data rate and perform the initialization sequences. The PWM outputs are held at a mute state until the master volume is set to a value other than mute via I2C. 5.2.
TAS5548 SLES270 – NOVEMBER 2012 5.2.3 www.ti.com Back-End Error (BKND_ERR) Back-end error is used to provide error management for back-end error conditions. Back-end error is a level-sensitive signal. Back-end error can be initiated by bringing the BKND_ERR terminal low for a minimum of five MCLK cycles. When BKND_ERR is brought low, the PWM sets either six or eight channels into the PWM back-end error state. This state is described in Section 4.1.
TAS5548 www.ti.com 5.2.4 SLES270 – NOVEMBER 2012 Speaker/Headphone Selector (HP_SEL) The HP_SEL terminal enables the headphone output or the speaker outputs. The headphone output receives the processed data output from DAP and PWM channels 1 and 2. In 6-channel configuration, this feature does not affect the two lineout channels. When low, the headphone output is enabled. In this mode, the speaker outputs are disabled. When high, the speaker outputs are enabled and the headphone is disabled.
TAS5548 SLES270 – NOVEMBER 2012 5.2.6 www.ti.com Power-Supply Volume Control (PSVC) The TAS5548 supports volume control both by conventional digital gain/attenuation and by a combination of digital and analog gain/attenuation. Varying the H-bridge power-supply voltage performs the analog volume control function.
TAS5548 www.ti.com 5.3 SLES270 – NOVEMBER 2012 Device Configuration Controls The TAS5548 provides a number of system configuration controls that can be set at initialization and set following a reset. • Channel configuration • Headphone configuration • Audio system configurations • Recovery from clock error • Power-supply volume-control enable • Volume and mute update rate • Modulation index limit • Master-clock and data-rate controls • Bank controls 5.3.
TAS5548 SLES270 – NOVEMBER 2012 D1 www.ti.com Sets number of speakers in the system, including possible line outputs D3–D1 must be configured for the audio system in the application, as shown in Table 5-6. Table 5-6. Audio System Configuration (General Control Register 0xE0) Audio System 5.3.3.1 D31–D4 D3 D2 D1 D0 6 channels or 5.1 not using PSVC 0 0 0 1 X 6 channels using PSVC 0 0 1 1 X 5.1 system using PSVC 0 0 1 1 X 8 channels or 7.
TAS5548 www.ti.com SLES270 – NOVEMBER 2012 Table 5-7. Volume Ramp Periods in ms SAMPLE RATE (kHz) NUMBER OF STEPS 5.3.7 44.1, 88.2, 176.4 32, 48, 96, 192 512 46.44 42.67 1024 92.88 85.33 2048 185.76 170.67 Modulation Index Limit PWM modulation is a linear function of the audio signal. When the audio signal is 0, the PWM modulation is 50%. When the audio signal increases toward full scale, the PWM modulation increases toward 100%.
TAS5548 SLES270 – NOVEMBER 2012 5.4.2 www.ti.com PLL Operation The TAS5548 uses two internal clocks generated by two internal phase-locked loops (PLLs), the digital PLL (DPLL) and the analog PLL (APLL). The APLL provides the reference clock for the PWM. The DPLL provides the reference clock for the digital audio processor and the control logic. The XTAL input provides the input reference clock for the APLL.
TAS5548 www.ti.com SLES270 – NOVEMBER 2012 6 System Power Controller 6.1 Energy Manager TAS5548 has an Energy Manager that can be used to monitor/control the overall energy in the system. The key features are: 1. There are separate controllers for Satellite (EMO1) and Sub (EMO2) channels. If EMO2 is not enabled, then the EMO1 pin is OR'd with the output of the subwoofer comparator. 2. The satellite channels participating in the energy estimation are selectable. For example, in the 5.
TAS5548 SLES270 – NOVEMBER 2012 6.2 www.ti.com Programming Energy Manager Energy Manager related registers are 0xBA to 0xBE. 0xB2 is a 16 byte averaging filter (alpha filter) for both satellite and sub channel. The scaling coefficients are 0xB3 to 0xBA that multiplies energy of each channel with a scaling factor. The threshold registers are (0xBB, 0xBC, 0xBD and 0xBE) and 0x10 for the results register. Table 6-1.
TAS5548 www.ti.com SLES270 – NOVEMBER 2012 7 Electrical Specifications 7.1 Absolute Maximum Ratings (1) Supply voltage, DVDD1 and DVDD2 –0.3 V to 3.9 V Supply voltage, AVDD and AVDD_PWM Input voltage –0.3 V to 3.9 V 3.3-V digital input –0.5 V to DVDD + 0.5 V 5-V tolerant (2) digital input ±20 μA IIK Input clamp current (VI < 0 or VI > 1.8 V IOK Output clamp current (VO < 0 or VO > 1.8 V) TA Operating free-air temperature Tstg (1) (2) 7.2 –0.
TAS5548 SLES270 – NOVEMBER 2012 7.5 www.ti.com Electrical Characteristics At recommended operating conditions - 25 °C Operating Temp, 3.3V Power Supplies with 48kHz input data unless otherwise specified PARAMETER VOH High-level output voltage VOL Low-level output voltage IOZ High-impedance output current IIL High-level input current MAX IOH = –0.55 mA 3.3-V TTL and 5-V tolerant (1) IOL = 4 mA 0.5 1.8-V LVCMOS (XTL_OUT) IOL = 0.75 mA 0.5 UNIT 2.4 V 1.44 V μA ±20 3.
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TAS5548 SLES270 – NOVEMBER 2012 7.7.2 www.ti.com Serial Audio Port Serial audio port slave mode over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS fSCLKIN SCLK input frequency MIN CL = 30 pF TYP 2.048 MAX UNIT 12.
TAS5548 www.ti.com SLES270 – NOVEMBER 2012 Timing Characteristics for I2C Interface Signals over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS STANDARD MODE MIN FAST MODE MAX MIN MAX 300 20 + 0.
TAS5548 SLES270 – NOVEMBER 2012 7.7.4 www.ti.com Reset Timing (RESET) Control signal parameters over recommended operating conditions (unless otherwise noted) PARAMETER tr(DMSTATE) Time to Non PWM Switching low tw(RESET) Pulse duration, RESET active tr(I2C_ready) Time to enable I2C MIN TYP MAX 400 400 UNIT ns None 5 ns ms Earliest time that PWM outputs could be enabled RESET t w(RESET) VALID t r (I2C_ready) t r (DMSTATE) 370 ns Determine SCLK rate and MCLK ratio. Enable via I 2C.
TAS5548 www.ti.com 7.7.6 SLES270 – NOVEMBER 2012 Back-End Error (BKND_ERR) Control signal parameters over recommended operating conditions (unless otherwise noted) PARAMETER MIN tw(ER) Pulse duration, BKND_ERR active tp(valid_low) Minimum amount of time that device asserts VALID low. tp(valid_high) I2C programmable to be between <1mS to 1.
TAS5548 SLES270 – NOVEMBER 2012 7.7.8 www.ti.com Headphone Select (HP_SEL) Control signal parameters over recommended operating conditions (unless otherwise noted) PARAMETER tw(HP_SEL) TYP Pulse duration, HP_SEL active td(VOL) Soft volume update time t(SW) Switchover time (1) MIN MAX 165 UNIT ms Defined by rate setting (1) ms 165 ms See the Volume, Treble, and Base Slew Rates Register (0xD0) section.Section 11.35.
TAS5548 www.ti.com 7.8 SLES270 – NOVEMBER 2012 Serial Audio Interface Control and Timing 7.8.1 Input I 2S Timing I2S timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCLK is low for the left channel and high for the right channel. A bit clock running at 64 fS is used to clock in the data. From the time the LRCLK signal changes state to the first bit of data on the data lines is a delay of one bit clock.
TAS5548 SLES270 – NOVEMBER 2012 7.8.2 www.ti.com Left-Justified Timing Left-justified (LJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 64 fS is used to clock in the data. The first bit of data appears on the data lines at the same time LRCLK toggles. The data is written MSB first and is valid on the rising edge of the bit clock.
TAS5548 www.ti.com 7.8.3 SLES270 – NOVEMBER 2012 Right-Justified Timing Right-justified (RJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 64 fS is used to clock in the data. The first bit of data appears on the data lines eight bit-clock periods (for 24-bit data) after LRCLK toggles.
TAS5548 SLES270 – NOVEMBER 2012 www.ti.com 7.11 10.6 LRCKO and SCLKO There are output pins for LRCLK output and SCK output. As the SDIN5 rate (which always follow internal sample rate) and the SDOUT rate (which is 44.1 kHz or 48 kHz) is different, the LRCLKO will be the internal sample rate (96 kHz or 192 kHz) when SDIN5 is activated (SDOUT is not available) and it will be 44.1 kHz or 48 kHz when SDOUT is available. The SCLKO will be always 64x LRCLKO. 8.
TAS5548 www.ti.com 8 SLES270 – NOVEMBER 2012 I2C Serial-Control Interface (Slave Addresses 0x36) The TAS5548 has a bidirectional I2C interface that is compatible with the Inter-IC (I2C) bus protocol and supports both 100-kbps and 400-kbps data transfer rates for single- and multiple-byte write and read operations. This is a slave-only device that does not support a multimaster bus environment or wait state insertion.
TAS5548 SLES270 – NOVEMBER 2012 8.2 www.ti.com Single- and Multiple-Byte Transfers The serial-control interface supports both single-byte and multiple-byte read/write operations for status registers and the general control registers associated with the PWM. However, for the DAP data processing registers, the serial-control interface supports only multiple-byte (four-byte) read/write operations.
TAS5548 www.ti.com 8.4 SLES270 – NOVEMBER 2012 Multiple-Byte Write A multiple-byte, data-write transfer is identical to a single-byte, data-write transfer except that multiple data bytes are transmitted by the master device to TAS5548, as shown in Figure 8-3. After receiving each data byte, the TAS5548 responds with an acknowledge bit.
TAS5548 SLES270 – NOVEMBER 2012 8.6 www.ti.com Single-Byte Read As shown in Figure 8-4, a single-byte, data-read transfer begins with the master device transmitting a start condition followed by the I2C device address and the read/write bit. For the data-read transfer, both a write and then a read are actually performed. Initially, a write is performed to transfer the address byte or bytes of the internal memory address to be read. As a result, the read/write bit is a 0.
TAS5548 www.ti.com SLES270 – NOVEMBER 2012 9 Application Recommendations / Settings 9.1 Device System Diagrams Typical applications for the TAS5548 are 6- to 8-channel audio systems such as DVD or AV receivers. Figure 9-1 shows the basic system diagram of the DVD receiver. Power Supply AM FM Tuner Texas Instruments Digital Audio Amplifier TAS5548 DVD Loader MPEG Decoder Front-Panel Controls B0012-03 Figure 9-1.
TAS5548 SLES270 – NOVEMBER 2012 LEFT SURROUND + − RIGHT + − PWM_M_1 PWM_P_1 PWM_HPML PWM_HPPL PWM_HPMR PWM_M_2 PWM_HPPR PWM_P_2 TAS5548 LEFT + − TI Power Stage PWM_M_3 PWM_P_4 PWM_P_3 TI Power Stage PWM_M_7 PWM_P_7 PWM_P_8 TI Power Stage PWM_M_5 PWM_P_5 RIGHT SURROUND + − PWM_M_5 PWM_P_5 PWM_M_6 PWM_P_6 PWM_P_6 PWM_M_6 TI Power Stage CENTER + − PWM_M_4 LEFT BACK SURROUND SUBWOOFER + − + − PWM_M_8 RIGHT BACK SURROUND − + www.ti.
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TAS5548 SLES270 – NOVEMBER 2012 www.ti.com Table 9-1.
TAS5548 www.ti.com 9.3 SLES270 – NOVEMBER 2012 Recommended Circuit Recommended external components for the TAS5548 are shown below HEADPHONE PWM OUT PWM_HPP_R PWM_HPM_R FROM CONTROLLER C3 C1 4700pfd/25V 0402 X7R C2 R3 470 0402 0.047ufd/16V 0402 X7R 470 0402 +3.3V +3.3V R1 R2 4.99K 0402 4.99K 0402 SDA C6 10.0ufd/10V 0603 X5R 0.1ufd/16V 0402 X7R GND C7 SCL R5 GND 15.0K 0402 1/16W GND 33pfd/50V 0402 COG C8 GND Y2 R6 12.288 MHz ABM8G 1.
TAS5548 SLES270 – NOVEMBER 2012 9.4 www.ti.com Startup Register Writes to get Audio Functioning By default, the device starts up with its outputs muted. The following writes should be used to bring it out of standby TAS5548 1. Exit Shutdown 0x03 = A0 2.
TAS5548 www.ti.com 10 SLES270 – NOVEMBER 2012 Serial-Control I2C Register Summary The TAS5548 slave write address is 0x36 and the read address is 0x37. See Serial-Control Interface Register Definitions, Section 11 for complete bit definitions. Note: Default stat is read immediately after device reset.
TAS5548 SLES270 – NOVEMBER 2012 www.ti.com I2C SUBADDRESS TOTAL BYTES 0x34 1 PWM_mux_ch1&2 See Table 11-20 & Table 11-21 01 0x35 1 PWM_mux_ch3&4 See Table 11-20 & Table 11-21 23 0x36 1 PWM_mux_ch5&6 See Table 11-20 & Table 11-21 45 0x37 1 PWM_mux_ch7&8 See Table 11-20 & Table 11-21 67 0x38 1 IC Delay Channel 0(BD Mode) See Section 11.19 80 0x39 1 IC Delay Channel 1(BD Mode) See Section 11.19 00 0x3A 1 IC Delay Channel 2(BD Mode) See Section 11.
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TAS5548 SLES270 – NOVEMBER 2012 I2C SUBADDRESS TOTAL BYTES 0xB2 16 REGISTER FIELDS DESCRIPTION OF CONTENTS DEFAULT STATE (hex) Energy Manager Averaging coefficients(Two 28 bit coefficients for satellite and sub-woofer) sat_channels_alpha[31:0], sat_channels_1-alpha[31:0] sub_channel_alpha[31:0], sub_channels_1-alpha[31:0] 0000 0000 0000 0000 Energy Manager Weighting co-efficients(28-bit coefficient for channel1) 5.
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TAS5548 SLES270 – NOVEMBER 2012 I2C SUBADDRESS TOTAL BYTES 0xF6 16 0xF7 REGISTER FIELDS DESCRIPTION OF CONTENTS DEFAULT STATE (hex) 192kHz Process Flow Output Mixer P1_to_opmix[3] (5.23). See 0000 0000 0000 0000 192kHz Process Flow Output Mixer P2_to_opmix[3] (5.23). See 0000 0000 0000 0000 192kHz Process Flow Output Mixer P3_to_opmix[3] (5.23). See 0080 0000 0000 0000 192kHz Process Flow Output Mixer P4_to_opmix[3] (5.23).
TAS5548 www.ti.com 11 SLES270 – NOVEMBER 2012 Serial-Control Interface Register Definitions Unless otherwise noted, the I2C register default values are in bold font. Note that u indicates unused/reserved bits. 11.1 General Status Register 0 (0x01) Table 11-1.
TAS5548 SLES270 – NOVEMBER 2012 www.ti.com 11.2 Error Status Register (0x02) Note that the error bits are sticky bits that are not cleared by the hardware. This means that the software must clear the register (write zeroes) and then read them to determine if there are any persistent errors. Bits D7-D4 are reserved. Table 11-2.
TAS5548 www.ti.com SLES270 – NOVEMBER 2012 11.4 System Control Register 2 (0x04) Bit D3 is reserved. Table 11-4.
TAS5548 SLES270 – NOVEMBER 2012 www.ti.com 11.6 Headphone Configuration Control Register (0x0D) Bit D0 is don't care. Table 11-6. Headphone Configuration Control Register Format D7 D6 D5 D4 D3 D2 D1 D0 0 – – – – – – – Disable back-end reset sequence for Headphone FUNCTION 1 – – – – – – – Enable back-end reset sequence for Headphone – 0 – – – – – – Valid is high when headphone PWM outputs are switching – 1 – – – – – – Valid low in Headphone mode.
TAS5548 www.ti.com SLES270 – NOVEMBER 2012 Table 11-8.
TAS5548 SLES270 – NOVEMBER 2012 www.ti.com 11.9 Energy Manager Status Register (0x10) These bits are sticky and will be cleared only when a '0' is written into these bits through I2C interface. Table 11-9.
TAS5548 www.ti.com SLES270 – NOVEMBER 2012 11.10 Automute Control Register (0x14) Table 11-10. Automute Control Register Format D7 D6 D5 D4 D3 D2 D1 D0 – – – – 0 0 0 0 Set input automute and output automute delay to 2.98 ms FUNCTION – – – – 0 0 0 1 Set input automute and output automute delay to 4.47 ms – – – – 0 0 1 0 Set input automute and output automute delay to 5.96 ms – – – – 0 0 1 1 Set input automute and output automute delay to 7.
TAS5548 SLES270 – NOVEMBER 2012 www.ti.com 11.11 Output Automute PWM Threshold and Back-End Reset Period Register (0x15) For more information on how to use this register, see Automute and Mute Channel Controls, Table 11-11.
TAS5548 www.ti.com SLES270 – NOVEMBER 2012 11.12 Modulation Index Limit Register (0x16, 0x17, 0x18, 0x19) Note that some power stages require a lower modulation limit than the default of 93.7%. Contact Texas Instruments for more details about the requirements for a particular power stage. Table 11-12. Modulation Limit Register Format Di+3 Di+2 Di+1 Di (i=0 or 4) LIMIT [DCLKs] MIN WIDTH [DCLKs] MODULATION INDEX 0 0 0 0 1 2 99.21% 0 0 0 1 2 4 98.43% 0 0 1 0 3 6 97.
TAS5548 SLES270 – NOVEMBER 2012 www.ti.com 11.13 AD Mode - 8 Interchannel Channel Delay & Global Offset Registers (0x1B to 0x23) Interchannel delay is used to distribute the switching current of each channel, to ease the peak power draw on the PSU. It's also used to control the intermodulation between the channels, therefore improving THD in some cases. DCLK is the oversampling clock of the PWM. DCLK on the TAS5548 will be constant, unless some AM avoidance modes are used.
TAS5548 www.ti.com SLES270 – NOVEMBER 2012 11.14 Special Low Z and Mid Z Ramp/Stop Period (0x24) This is also the delay period for delayed start/stop with legacy LowZ sequences. If register 0x25 is programmed for special LowZ sequence, the time above is the PWM ramp up period. If it is programmed for MidZ, the time above is the PWM stop period. D7 D6 D5 D4 D3 D2 D1 D0 – – – 0 0 – – – No Ramp/Stop period FUNCTION – – – 0 1 0 0 0 14.
TAS5548 SLES270 – NOVEMBER 2012 www.ti.com Table 11-17.
TAS5548 www.ti.com SLES270 – NOVEMBER 2012 Table 11-21. PWM Registers Format D6/D2 D5/D1 D4/D0 FUNCTION 0 0 0 Select channel 1 0 0 1 Select channel 2 0 1 0 Select channel 3 0 1 1 Select channel 4 1 0 0 Select channel 5 1 0 1 Select channel 6 1 1 0 Select channel 7 1 1 1 Select channel 8 11.
TAS5548 SLES270 – NOVEMBER 2012 www.ti.com 11.20 Input Mixer Registers, Channels 1–8 (0x41–0x48) Input mixers 1, 2, 3, 4, 5, 6, 7, and 8 are mapped into registers 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, and 0x48, respectively. Each gain coefficient is in 28-bit (5.23) format, so 0x80 0000 is a gain of 1. Each gain coefficient is written as a 32-bit word with the upper four bits reserved. For eight gain coefficients, the total is 32 bytes. There is no negative value available.
TAS5548 www.ti.com SLES270 – NOVEMBER 2012 Table 11-23.
TAS5548 SLES270 – NOVEMBER 2012 www.ti.com 11.21 Bass Mixer Registers (0x49–0x50) Registers 0x49–0x50 provide configuration control for bass mangement. Each gain coefficient is in 28-bit (5.23) format, so 0x80 0000 is a gain of 1. Each gain coefficient is written as a 32-bit word with the upper four bits reserved. There is no negative value available. The mixer cannot phase invert. Table 11-24.
TAS5548 www.ti.com SLES270 – NOVEMBER 2012 Each gain coefficient is in 28-bit (5.23) format, so 0x80 0000 is a gain of 1. Each gain coefficient is written as a 32-bit word with the upper four bits not used. Table 11-26. Contents of One 20-Byte Biquad Filter Register (Default = All-Pass) DESCRIPTION DEFAULT GAIN COEFFICIENT VALUES REGISTER FIELD CONTENTS DECIMAL HEX b0 coefficient u[31:28], b0[27:24], b0[23:16], b0[15:8], b0[7:0] 1.
TAS5548 SLES270 – NOVEMBER 2012 www.ti.com 11.25 DRC1 Control Register CH1-7 (0x96) – Write DRC Control selects which channels contribute to the expansion/compression evaluation using DRC1. The evaluation is global such that if one signal forces compression all DRC1 signals will be in compression. Table 11-29.
TAS5548 www.ti.com SLES270 – NOVEMBER 2012 11.26 DRC2 Control Register CH8 (0x97) – Write Register DRC Control selects which channels contribute to the expansion/compression evaluation using DRC2. The evaluation is global such that if one signal forces compression all DRC2 signals will be in compression. Table 11-30.
TAS5548 SLES270 – NOVEMBER 2012 www.ti.com 11.27 DRC1 Data Registers (0x98–0x9C) DRC1 applies to channels 1, 2, 3, 4, 5, 6, and 7. Table 11-31.
TAS5548 www.ti.com SLES270 – NOVEMBER 2012 11.28 DRC2 Data Registers (0x9D–0xA1) DRC2 applies to channel 8. Table 11-32.
TAS5548 SLES270 – NOVEMBER 2012 • www.ti.com DAP channel 6 is mapped though the 8×2 crossbar mixer (0xAF) to PWM channel 6 Note that the pass-through output mixer configuration (0xD0 bit 30 = 1) is recommended. Using the remapped output mixer configuration (0xD0 bit 30 = 0) increases the complexity of using some features such as volume and mute. Total data per register is 8 bytes. The default gain for each selected channel is 1 (00 80 00 00) and 0.5 value is (00 40 00 00) value. The format is 5.
TAS5548 www.ti.com SLES270 – NOVEMBER 2012 11.31 8×3 Output Mixer Registers (0xB0–0xB1) The pass-through output mixer setting is: • DAP channel 7 is mapped though the 8×3 crossbar mixer (0xB0) to PWM channel 7 • DAP channel 8 is mapped though the 8×3 crossbar mixer (0xB1) to PWM channel 8 The default gain is 1 (00 80 00 00), 0.5 value is (00 40 00 00). Format is 5.23 Total data per register is 12 bytes. The default gain for each selected channel is 1 (0x0080 0000). Table 11-36.
TAS5548 SLES270 – NOVEMBER 2012 www.ti.com Table 11-37.
TAS5548 www.ti.com SLES270 – NOVEMBER 2012 11.32 ASRC Registers (0xC3-C5) Table 11-39.
TAS5548 SLES270 – NOVEMBER 2012 www.ti.com Table 11-40.
TAS5548 www.ti.com SLES270 – NOVEMBER 2012 Table 11-41.
TAS5548 SLES270 – NOVEMBER 2012 www.ti.com 11.33 Auto Mute Behavior (0xCC) Table 11-42. Auto Mute Behavior D31 D30 D29 D28 D27 D26 D25 D24 FUNCTION Reserved D23 D22 D21 D20 D19 D18 D17 D16 FUNCTION Reserved D15 D14 D7 D13 D6 D12 D5 D11 D4 D10 D3 D9 D2 D1 D8 FUNCTION 0 Disable noise shaper on auto mute 1 Do not disable noise shaper on auto mute D0 FUNCTION 0 Do not stop PWM on auto mute (Stay at duty 50:50) 1 Stop PWM on auto mute 11.
TAS5548 www.ti.com SLES270 – NOVEMBER 2012 Table 11-45. Treble and Bass Gain Step Size (Slew Rate) (continued) D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 1 1 1 1 1 Default rate - Updates every 1.31 ms (63 LRCLKs at 48 kHz). This is the maximum constant time that can be set for all sample rates. FUNCTION 1 1 1 1 1 1 1 1 Maximum rate – Updates every 5.08 ms (every 255 LRCLKs at 48 kHz) Note: Once the volume command is given, no I2C commands should be issued until volume ramp has finished.
TAS5548 SLES270 – NOVEMBER 2012 www.ti.com 11.36 Volume Registers (0xD1–0xD9) Channels 1, 2, 3, 4, 5, 6, 7, and 8 are mapped into registers 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, and 0xD8, respectively. The default volume for all channels is 0 dB. Master volume is mapped into register 0xD9. The default for the master volume is mute. Bits D31–D12 are reserved. D9-D0 are the volume index, their values can be calculated from Table 11-47. Table 11-46.
TAS5548 www.ti.com SLES270 – NOVEMBER 2012 Table 11-47. Master and Individual Volume Controls VOLUME INDEX (H) GAIN/INDEX(dB) 001 17.75 002 17.5 003 17.25 004 17 005 16.75 006 16.5 007 16.25 008 16 009 15.75 00A 15.5 00B 15.25 00C 15 00D 14.75 00E 14.5 00F 14.25 010 14 ... ... 044 1 045 0.75 046 0.5 047 0.25 048 0 049 –0.25 04A –0.5 04B –0.75 04C –1 ... ... 240 –126 241 –126.25 242 –126.5 243 –126.
TAS5548 SLES270 – NOVEMBER 2012 www.ti.com 11.37 Bass Filter Set Register (0xDA) To use the bass and treble function, the bass and treble bypass registers (0x89–0x90) must be configured as inline (default is bypass). See Table 11-27 to configure the Bass Filter mode as inline or bypass. Table 11-48.
TAS5548 www.ti.com SLES270 – NOVEMBER 2012 Table 11-51. Channels 7, 2, and 1 (Center, Right Front, and Left Front) D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION 0 0 0 0 0 0 0 0 No change 0 0 0 0 0 0 0 1 Bass filter set 1 0 0 0 0 0 0 1 0 Bass filter set 2 0 0 0 0 0 0 1 1 Bass filter set 3 0 0 0 0 0 1 0 0 Bass filter set 4 0 0 0 0 0 1 0 1 Bass filter set 5 0 0 0 0 0 1 1 0 Illegal 0 0 0 0 0 1 1 1 Illegal 11.
TAS5548 SLES270 – NOVEMBER 2012 www.ti.com 11.39 Treble Filter Set Register (0xDC) Bits D31–D27 are reserved. To use the bass and treble function, the bass and treble bypass registers (0x89 - 0x90) must be configured as inline (enabled). See Table 11-27 to configure the Treble Filter mode as inline or bypass. Table 11-54.
TAS5548 www.ti.com SLES270 – NOVEMBER 2012 Bits D7–D3 are reserved. Table 11-57.
TAS5548 SLES270 – NOVEMBER 2012 www.ti.com 11.41 AM Mode Register (0xDE) Bits D31–D25 and D23-D21 are reserved. BCD = Binary Coded Decimal. Table 11-60.
TAS5548 www.ti.com SLES270 – NOVEMBER 2012 11.42 PSVC Range Register (0xDF) Bits D31–D2 are zero. Table 11-63. PSVC Range Register Format D31–D2 D1 D0 0 0 0 12.04-dB control range for PSVC FUNCTION 0 0 1 18.06-dB control range for PSVC 0 1 0 24.08-dB control range for PSVC 0 1 1 Ignore – retain last value 11.43 General Control Register (0xE0) Bits D31–D4 are zero. Bit D0 is reserved. Table 11-64.
TAS5548 SLES270 – NOVEMBER 2012 www.ti.com negative values 08xx xxxx will invert the signal amplitude Table 11-66. THD Manager Configuration I2C SUBADDRESS TOTAL BYTES 0xE9 4 prescale THD Manager (pre) - provide boost if desired to clip 0080 0000 0xEA 4 postscale THD Manager (post) - cut clipping signal to final level 0080 0000 REGISTER Fields DESCRIPTION OF CONTENTS DEFAULT STATE 11.46 SDIN5 Input Mixer (0xEC–0xF3) Each gain coefficient is in 28-bit (5.
TAS5548 www.ti.com SLES270 – NOVEMBER 2012 11.47 192kHZ Process Flow Output Mixer (0xF4–0xF7) Each gain coefficient is in 28-bit (5.23) format, so 0x80 0000 is a gain of 1. Each gain coefficient is written as a 32-bit word with the upper four bits not used. For eight gain coefficients, the total is 32 bytes. Table 11-68.
TAS5548 SLES270 – NOVEMBER 2012 www.ti.com 11.48 192kHz Dolby Downmix Coefficients (0xFB & 0xFC) Each gain coefficient is in 28-bit (5.23) format, so 0x80 0000 is a gain of 1. Each gain coefficient is written as a 32-bit word with the upper four bits not used. For eight gain coefficients, the total is 32 bytes. Table 11-69. 192kHz Dolby Downmix Coefficients I2C SUBADDRESS TOTAL BYTES REGISTER Fields 0xFB 16 dolby_COEF1L (D1_L) 192kHz SDIN1-left to SDOUT-left down-mix coefficient (default = 1/3.
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PACKAGE MATERIALS INFORMATION www.ti.com 1-Dec-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TAS5548DCAR Package Package Pins Type Drawing SPQ HTSSOP 2000 DCA 56 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 24.4 Pack Materials-Page 1 8.6 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 15.6 1.8 12.0 24.
PACKAGE MATERIALS INFORMATION www.ti.com 1-Dec-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TAS5548DCAR HTSSOP DCA 56 2000 367.0 367.0 45.
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