Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLinear ICsLinear IC - Audio amplifier 1-channel (mono) or 2-channel (stereo) Class D HTQFP 64 (14x14

PurePath

Class-G Power Supply

Ref. Design

110 VAC 240 VAC®

25 V–50 V

ANALOG

AUDIO

INPUT

12 V

PurePath

TAS5630B

(2.1 Configuration)

♫♪

3 OPA1632´

±15 V

TAS5630B

www.ti.com

SLES217C –NOVEMBER 2010–REVISED SEPTEMBER 2012

300-W STEREO / 400-W MONO PurePath™ HD ANALOG-INPUT POWER STAGE

Check for Samples: TAS5630B

FEATURES

APPLICATIONS

• PurePath™ HD Enabled Integrated Feedback

• Mini Combo System

Provides:

• AV Receivers

– Signal Bandwidth up to 80 kHz for High-

• DVD Receivers

Frequency Content From HD Sources

• Active Speakers

– Ultralow 0.03% THD at 1 W into 4 Ω

– Flat THD at all Frequencies for Natural DESCRIPTION

Sound

The TAS5630B is a high-performance analog-input

class-D amplifier with integrated closed-loop

– 80-dB PSRR (BTL, No Input Signal)

feedback technology (known as PurePath HD

– >100-dB (A-weighted) SNR

technology) with the ability to drive up to 300 W

(1)

– Click- and Pop-Free Start-Up

stereo into 4-Ω to 8-Ω speakers from a single 50-V

supply.

• Multiple Configurations Possible on the Same

PCB With Stuffing Options:

PurePath HD technology enables traditional AB-

– Mono Parallel Bridge-Tied Load (PBTL)

amplifier performance (<0.03% THD) levels while

providing the power efficiency of traditional class-D

– Stereo Bridge-Tied Load (BTL)

amplifiers.

– 2.1 Single-Ended Stereo Pair and Bridge-

Unlike traditional class-D amplifiers, the distortion

Tied Load Subwoofer

curve does not increase until the output levels move

– Quad Single-Ended Outputs

into clipping. PurePath HD™

• Total Output Power at 10% THD+N

PurePath HD technology enables lower idle losses,

– 400 W in Mono PBTL Configuration

making the device even more efficient. Coupled with

– 300 W per Channel in Stereo BTL

TI’s class-G power-supply reference design for

Configuration

TAS563x, industry-leading levels of efficiency can be

achieved.

– 145 W per Channel in Quad Single-Ended

Configuration

• High-Efficiency Power Stage (>88%) With 60-

mΩ Output MOSFETs

• Two Thermally Enhanced Package Options:

– PHD (64-Pin QFP)

– DKD (44-Pin PSOP3)

• Self-Protection Design (Including

Undervoltage, Overtemperature, Clipping, and

Short-Circuit Protection) With Error Reporting

• EMI Compliant When Used With

Recommended System Design

(1) Achievable output power levels are dependent on the thermal

configuration of the target application. A high-performance

thermal interface material between the exposed package heat

slug and the heat sink should be used to achieve high output

power levels.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PurePath HD is a trademark of Texas Instruments.

3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (36 pages)

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TAS5630B www.ti.com SLES217C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 300-W STEREO / 400-W MONO PurePath™ HD ANALOG-INPUT POWER STAGE Check for Samples: TAS5630B FEATURES APPLICATIONS • • • • • 1 23 • • • • • • PurePath™ HD Enabled Integrated Feedback Provides: – Signal Bandwidth up to 80 kHz for HighFrequency Content From HD Sources – Ultralow 0.
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TAS5630B SLES217C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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TAS5630B www.ti.
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TAS5630B SLES217C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) VALUE UNIT VDD to AGND –0.3 to 13.2 V GVDD to AGND –0.3 to 13.2 V PVDD_X to GND_X (2) –0.3 to 69 V OUT_X to GND_X (2) –0.3 to 69 V BST_X to GND_X (2) –0.3 to 82.2 V BST_X to GVDD_X (2) –0.3 to 69 V VREG to AGND –0.3 to 4.2 V GND_X to GND –0.3 to 0.3 V GND_X to AGND –0.3 to 0.
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TAS5630B www.ti.com SLES217C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 PIN FUNCTIONS PIN Function (1) DESCRIPTION 10 P Analog ground 43 P HS bootstrap supply (BST), external 0.033-μF capacitor to OUT_A required. 41 34 P HS bootstrap supply (BST), external 0.033-μF capacitor to OUT_B required. 40 33 P HS bootstrap supply (BST), external 0.033-μF capacitor to OUT_C required. BST_D 27 24 P HS bootstrap supply (BST), external 0.033-μF capacitor to OUT_D required.
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TAS5630B SLES217C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 www.ti.com PIN FUNCTIONS (continued) PIN NAME PVDD_D READY Function (1) DESCRIPTION PHD NO. DKD NO. 30, 31 25, 26 P Power-supply input for half-bridge D requires close decoupling of 0.01-μF capacitor in parallel with 2.2-μF capacitor to GND_D.
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TAS5630B www.ti.
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TAS5630B SLES217C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 www.ti.
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TAS5630B www.ti.com SLES217C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 AUDIO CHARACTERISTICS (BTL) PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 50 V, GVDD_X = 12 V, RL = 4 Ω, fS = 400 kHz, ROC = 22 kΩ, TC = 75°C; output filter: LDEM = 7 μH, CDEM = 680 nF, MODE = 010, unless otherwise noted.
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TAS5630B SLES217C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 www.ti.com AUDIO SPECIFICATION (PBTL) PCB and system configuration are in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 50 V, GVDD_X = 12 V, RL = 3 Ω, fS = 400 kHz, ROC = 22 kΩ, TC = 75°C; output filter: LDEM = 7 μH, CDEM = 1.5 μF, MODE = 101-10, unless otherwise noted.
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TAS5630B www.ti.com SLES217C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 ELECTRICAL CHARACTERISTICS (continued) PVDD_X = 50 V, GVDD_X = 12 V, VDD = 12 V, TC (Case temperature) = 75°C, fS = 400 kHz, unless otherwise specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT I/O PROTECTION Undervoltage protection limit, GVDD_x and VDD Vuvp,G Vuvp,hyst (1) 9.5 V 0.
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TAS5630B SLES217C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 www.ti.com TYPICAL CHARACTERISTICS, BTL CONFIGURATION TOTAL HARMONIC+NOISE vs OUTPUT POWER OUTPUT POWER vs SUPPLY VOLTAGE 340 10 THD+N − Total Harmonic Distortion + Noise − % 4Ω 6Ω 8Ω 4Ω 6Ω 8Ω 320 300 280 260 PO − Output Power − W 1 0.1 240 220 200 180 160 140 120 100 80 60 40 0.01 0.
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TAS5630B www.ti.
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TAS5630B SLES217C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 www.ti.com TYPICAL CHARACTERISTICS, SE CONFIGURATION 1 Channel Driven TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER OUTPUT POWER vs SUPPLY VOLTAGE 170 2Ω 3Ω 4Ω 2Ω 3Ω 4Ω 160 150 140 130 1 PO − Output Power − W THD+N − Total Harmonic Distortion + Noise − % 10 0.1 120 110 100 90 80 70 60 50 40 30 20 0.01 0.
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TAS5630B www.ti.com SLES217C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 TYPICAL CHARACTERISTICS, PBTL CONFIGURATION TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER OUTPUT POWER vs SUPPLY VOLTAGE 500 3Ω 4Ω 6Ω 8Ω 3Ω 4Ω 6Ω 8Ω 450 400 1 PO − Output Power − W THD+N − Total Harmonic Distortion + Noise − % 10 0.1 350 300 250 200 150 100 50 0.01 TC = 75°C THD+N at 10% TC = 75°C 0.
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TAS5630B SLES217C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 www.ti.com APPLICATION INFORMATION PCB MATERIAL RECOMMENDATION FR-4 2-oz. (70-μm) glass epoxy material is recommended for use with the TAS5630B. The use of this material can provide for higher power output, improved thermal performance, and better EMI margin (due to lower PCB trace resistance). PVDD CAPACITOR RECOMMENDATION The large capacitors used in conjunction with each full bridge are referred to as the PVDD capacitors.
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R_RIGHT_N IN_RIGHT_P IN_LEFT_N IN_LEFT_P /RESET 10uF C16 10uF C14 10uF C12 10uF C10 C17 100pF C15 100pF C13 100pF C11 100pF C18 100pF READY /CLIP /OTW2 /OTW1 /SD OSC_IO- OSC_IO+ 100R R13 100R R12 100R R11 100R R10 100R R18 GND VREG GND R19 47k GND GND GND GND GND 10k R21 100nF C22 VREG 1nF C21 4.7nF 22.
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READY /CLIP /OTW2 /OTW1 /SD OSC_IO- OSC_IO+ IN_N IN_P /RESET 10uF 10uF 100R 100R 100R GND GND GND 100pF 100pF 100pF GND VREG 47k VREG GND GND GND GND GND 10k 100nF 1nF 4.7nF 22.
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READY /CLIP /OTW2 /OTW1 /SD OSC_IO- OSC_IO+ IN_D IN_C IN_B IN_A /RESET Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: TAS5630B 147kW 165kW 187kW 191kW 50V 49V 48V <48V GND GND GND GND R_COMP 100R 100R 100R GND 100pF 100pF 100pF 100pF 100pF PVDD PVDD C A Submit Documentation Feedback 470uF 50V 470uF 50V 470uF 50V 470uF 50V GND GND GND GND GND GND GND R_COMP R_COMP 10k 1% 10k 1% 10k 1% 10k 1% 10k 100nF 1nF 10nF 22.
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READY /CLIP /OTW2 /OTW1 /SD OSC_IO- OSC_IO+ IN_RIGHT IN_LEFT IN_CENTER_N IN_CENTER_P /RESET 10uF 10uF 10uF 10uF 100R 100R 100R 100R 100R GND GND GND GND GND 100pF 100pF 100pF 100pF 100pF 47k VREG GND GND GND GND GND 10k 100nF VREG 1nF 10nF 22.
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Copyright © 2010–2012, Texas Instruments Incorporated Product Folder Links: TAS5630B READY /OTW /SD OSC_IO- 10uF 10uF 10uF 10uF 100R R60 100R R53 100R R54 100R R45 100R R13 C81 100pF C80 100pF C79 100pF C82 100pF GND C78 100pF VREG R44 47k GND GND GND GND GND GND R20 10k C86 100nF GND GND VREG 22 21 20 19 18 17 16 15 14 13 12 11 9 8 7 6 5 4 3 2 1 10 VREG GND 1nF GND C35 100nF C42 C85 4.
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TAS5630B SLES217C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 www.ti.com THEORY OF OPERATION POWER SUPPLIES To facilitate system design, the TAS5630B needs only a 12-V supply in addition to the (typical) 50-V power-stage supply. An internal voltage regulator provides suitable voltage levels for the digital and low-voltage analog circuitry. Additionally, all circuitry requiring a floating voltage supply, e.g.
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TAS5630B www.ti.com SLES217C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 ERROR REPORTING The SD, OTW, OTW1 and OTW2 pins are active-low, open-drain outputs. Their function is for protection-mode signaling to a PWM controller or other system-control device. Any fault resulting in device shutdown is signaled by the SD pin going low. Likewise, OTW and OTW2 go low when the device junction temperature exceeds 125°C and OTW1 goes low when the junction temperature exceeds 100°C (see the following table).
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TAS5630B SLES217C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 www.ti.com filter. The typical duration is <15 ms/μF. While the PPSC detection is in progress, SD is kept low, and the device does not react to changes applied to the RESET pins. If no shorts are present the PPSC detection passes, and SD is released, a device reset does not start a new PPSC detection. PPSC detection is enabled in BTL and PBTL output configurations; the detection is not performed in SE mode.
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TAS5630B www.ti.com SLES217C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 The VREG pin is not recommended to be used as a voltage source for external circuitry. Click and Pop in SE-Mode The BTL startup has low click and pop due to the trimmed output dc offset, see the AUDIO CHARACTERISTICS (BTL) table.
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TAS5630B SLES217C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 www.ti.com Note T1: PVDD bulk decoupling capacitors C60–C64 should be as close as possible to the PVDD_X and GND_X pins; the heat sink sets the distance. Wide traces should be routed on the top layer with direct connection to the pins and without going through vias. No vias or traces should be blocking the current path. Note T2: Close decoupling of PVDD with low impedance X7R ceramic capacitors is placed under the heat sink and close to the pins.
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TAS5630B www.ti.com SLES217C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 Note B1: It is important to have a direct-low impedance return path for high current back to the power supply. Keep impedance low from top to bottom side of PCB through a lot of ground vias. Note B2: Bootstrap low-impedance X7R ceramic capacitors placed on bottom side provide a short, low-inductance current loop. Note B3: Return currents from bulk capacitors and output filter capacitors Figure 20.
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TAS5630B SLES217C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 www.ti.com REVISION HISTORY Changes from Original (November 2010) to Revision A Page • Changed Title From: 600-W MONO To 400-W MONO ........................................................................................................ 1 • Changed Feature From: 600 W per Channel in Mono PBTL Configuration To: 400 W per Channel in Mono PBTL Configuration .........................................................................................
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) TAS5630BDKDR HSSOP DKD 44 500 330.0 24.4 TAS5630BPHDR HTQFP PHD 64 1000 330.0 24.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 14.7 16.4 4.0 20.0 24.0 Q1 17.0 17.0 1.5 20.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TAS5630BDKDR HSSOP DKD TAS5630BPHDR HTQFP PHD 44 500 367.0 367.0 45.0 64 1000 367.0 367.0 45.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.