Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLinear ICsLinear IC - Audio amplifier 1-channel (mono) or 2-channel (stereo) Class D HTQFP 64 (14x14

TAS5630

PurePath

TAS5631B

TAS5518C

Digital PWM

Processor

DIGITAL

AUDIO

INPUT

♫♪

TAS5631B

www.ti.com

SLES263C –NOVEMBER 2010–REVISED SEPTEMBER 2012

300-W STEREO / 400-W MONO PurePath™ HD DIGITAL-INPUT POWER STAGE

Check for Samples: TAS5631B

FEATURES

APPLICATIONS

• PurePath™ HD Enabled Integrated Feedback

• Mini Combo System

Provides:

• AV Receivers

– Signal Bandwidth up to 80 kHz for High-

• DVD Receivers

Frequency Content From HD Sources

• Active Speakers

– Ultralow 0.03% THD at 1 W Into 4 Ω

– Flat THD at All Frequencies for Natural DESCRIPTION

Sound

The TAS5631B is a high-performance PWM input

class-D amplifier with integrated closed-loop

– 80-dB PSRR (BTL, No Input Signal)

feedback technology (known as PurePath HD

– >100-dB (A-weighted) SNR

technology) with the ability to drive up to 300 W

(1)

– Click- and Pop-Free Start-Up

stereo into 4-Ω to 8-Ω speakers from a single 50-V

supply.

• Multiple Configurations Possible on the Same

PCB With Stuffing Options:

PurePath HD technology enables traditional AB-

– Mono Parallel Bridge-Tied Load (PBTL)

amplifier performance (<0.03% THD) levels while

providing the power efficiency of traditional class-D

– Stereo Bridge-Tied Load (BTL)

amplifiers.

– 2.1 Single-Ended Stereo Pair and Bridge-

Unlike traditional class-D amplifiers, the distortion

Tied Load Subwoofer

curve does not increase until the output levels move

– Quad Single-Ended Outputs

into clipping. PurePath HD™

• Total Output Power at 10% THD+N

PurePath HD technology enables lower idle losses,

– 400 W per Channel in Mono PBTL

making the device even more efficient.

Configuration

– 300 W per Channel in Stereo BTL

Note 1. Achievable output power levels are

Configuration

dependent on the thermal configuration of the target

– 145 W per Channel in Quad Single-Ended

application. A high-performance thermal interface

Configuration

material between the package exposed heat slug

and the heat sink should be used to achieve high

• High-Efficiency Power Stage (>88%) With 60-

output-power levels.

mΩ Output MOSFETs

• Two Thermally Enhanced Package Options:

– PHD (64-Pin QFP)

– DKD (44-Pin PSOP3)

• Self-Protection Design (Including

Undervoltage, Overtemperature, Clipping, and

Short-Circuit Protection) With Error Reporting

• EMI Compliant When Used With

Recommended System Design

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PurePath HD is a trademark of Texas Instruments.

3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (37 pages)

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TAS5631B www.ti.com SLES263C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 300-W STEREO / 400-W MONO PurePath™ HD DIGITAL-INPUT POWER STAGE Check for Samples: TAS5631B FEATURES APPLICATIONS • • • • • 1 23 • • • • • • PurePath™ HD Enabled Integrated Feedback Provides: – Signal Bandwidth up to 80 kHz for HighFrequency Content From HD Sources – Ultralow 0.
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TAS5631B SLES263C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DEVICE INFORMATION Pin Assignment Both package types contains a heat slug that is located on the top side of the device for convenient thermal coupling to the heat sink.
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TAS5631B www.ti.
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TAS5631B SLES263C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) TAS5631B UNIT VDD to AGND –0.3 to 13.2 V GVDD to AGND –0.3 to 13.2 V PVDD_X to GND_X (2) –0.3 to 69 V PVDD_X to GND_X; DC voltage -0.3 to 57 V OUT_X to GND_X (2) –0.3 to 69 V –0.3 to 82.2 V BST_X to GVDD_X (2) –0.3 to 69 V VREG to AGND –0.3 to 4.2 V GND_X to GND –0.3 to 0.3 V GND_X to AGND –0.3 to 0.
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TAS5631B www.ti.com SLES263C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 PIN FUNCTIONS PIN Function (1) DESCRIPTION 10 P Analog ground 43 P HS bootstrap supply (BST); external 0.033-μF capacitor to OUT_A required 41 34 P HS bootstrap supply (BST); external 0.033-μF capacitor to OUT_B required BST_C 40 33 P HS bootstrap supply (BST); external 0.033-μF capacitor to OUT_C required BST_D 27 24 P HS bootstrap supply (BST); external 0.
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TAS5631B SLES263C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 www.ti.com PIN FUNCTIONS (continued) PIN NAME PHD NO. DKD NO. VREG 9 11 Function (1) P DESCRIPTION Digital regulator supply filter pin requires 0.1-μF capacitor to AGND.
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TAS5631B www.ti.
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TAS5631B SLES263C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 www.ti.com AUDIO CHARACTERISTICS (BTL) Audio performance is recorded as a chipset consisting of a TAS5518 PWM processor (modulation index limited to 97.7%) and a TAS5631B power stage. PCB and system configurations are in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 50 V, GVDD_X = 12 V, RL = 4 Ω, fS = 384 kHz, ROC = 22 kΩ, TC = 75°C; output filter: LDEM = 10 μH, CDEM = 680 nF, MODE = 000, unless otherwise noted.
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TAS5631B www.ti.com SLES263C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 AUDIO SPECIFICATION (PBTL) Audio performance is recorded as a chipset consisting of a TAS5086 PWM processor (modulation index limited to 97.7%) and a TAS5631B power stage. PCB and system configurations are in accordance with recommended guidelines. Audio frequency = 1 kHz, PVDD_X = 50 V, GVDD_X = 12 V, RL = 3 Ω, fS = 384 kHz, ROC = 22 kΩ, TC = 75°C; output filter: LDEM = 10 μH, CDEM = 680 nF, MODE = 100-00, unless otherwise noted.
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TAS5631B SLES263C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 www.ti.com ELECTRICAL CHARACTERISTICS PVDD_X = 50V, GVDD_X = 12 V, VDD = 12V, TC (case temperature) = 75°C, fS = 384 kHz, unless otherwise specified.
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TAS5631B www.ti.com SLES263C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 TYPICAL CHARACTERISTICS, BTL CONFIGURATION TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER OUTPUT POWER vs SUPPLY VOLTAGE 10 320 THD+N − Total Harmonic Distortion + Noise − % 4Ω 6Ω 8Ω 4Ω 6Ω 8Ω 300 280 260 240 PO − Output Power − W 1 0.1 220 200 180 160 140 120 100 80 60 40 0.01 0.005 0.02 0.1 1 10 100 TC = 75°C THD+N at 10% 20 TC = 75°C 0 400 25 30 PO − Output Power − W Figure 1. Figure 2.
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TAS5631B SLES263C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 www.ti.
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TAS5631B www.ti.com SLES263C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 TYPICAL CHARACTERISTICS, SE CONFIGURATION 1 Channel Driven TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER OUTPUT POWER vs SUPPLY VOLTAGE 160 2Ω 3Ω 4Ω 2Ω 3Ω 4Ω 150 140 130 120 PO − Output Power − W THD+N − Total Harmonic Distortion + Noise − % 10 1 0.1 110 100 90 80 70 60 50 40 30 20 0.01 0.02 0.
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TAS5631B SLES263C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 www.ti.com TYPICAL CHARACTERISTICS, PBTL CONFIGURATION TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER OUTPUT POWER vs SUPPLY VOLTAGE 500 3Ω 4Ω 6Ω 8Ω 3Ω 4Ω 6Ω 8Ω 450 400 1 PO − Output Power − W THD+N − Total Harmonic Distortion + Noise − % 10 0.1 350 300 250 200 150 100 0.01 50 TC = 75°C THD+N at 10% TC = 75°C 0.003 0.02 0.
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TAS5631B www.ti.com SLES263C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 APPLICATION INFORMATION PCB MATERIAL RECOMMENDATION FR-4 2-oz. (70 μm) glass epoxy material is recommended for use with the TAS5631B. The use of this material can provide for higher power output, improved thermal performance, and better EMI margin (due to lower PCB trace resistance). PVDD CAPACITOR RECOMMENDATION The large capacitors used in conjunction with each full bridge are referred to as the PVDD capacitors.
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TAS5631B SLES263C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 www.ti.com SYSTEM DESIGN RECOMMENDATIONS The following schematics and PCB layouts illustrate best practices in the use of the TAS5631B. GVDD/VDD (+12V) 2 10 100nF 100R 11 R_RIGHT_N 2 R13 VREG 1 12 13 100R 14 15 2 1 2 2 1 PVDD_C TEST OUT_C NC OUT_C NC GND_C /SD GND_C /OTW1 GND_D 38 C62 2.2uF 36 1 2 2 2 1 GND GND GND 2 R74 3.3R GND C78 10nF GND GND OUT_RIGHT_P R72 3.
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TAS5631B www.ti.com SLES263C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 3.3R 1 VDD (+12V) 2 GVDD (+12V) 1 1 GND 12 2 GND_A PVDD_A PVDD_A OUT_A BST_A OUT_A GVDD_A GVDD_B GND GND NC NC NC NC 1 1 2 1uF 250V 33nF 10uH 1 2 2 2 1 + 10nF 63V GND - 1 2 1 1nF 63V 2 2.2uF 63V 37 36 2 1 38 GND 10nF 63V 1 1 39 1 2 1 2 1 2 40 3.3R 35 35 34 OUT_LEFT_M GND 33 1 2 32 1000uF 63V 1 31 31 BST_D OUT_D 30 30 29 29 28 28 27 27 17 1nF 63V 41 2 GND_D 3.
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TAS5631B SLES263C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 www.ti.com 3.3R 1 VDD (+12V) 2 1 1 1 1 3.3R 1 2 33nF 1 2 GVDD (+12V) 100nF 2 2 10uH 1 GNDGND 1 VREG 51 49 50 52 55 54 53 56 57 58 59 61 62 60 63 6.3V GND 12 GND_A PVDD_A OUT_A OUT_A BST_A GVDD_A GVDD_B GND NC GND PVDD_A PVDD_C INPUT_D PVDD_C TEST 2 B PVDD 1 42 42 2 47uF 63V 39 39 38 38 2.2uF 63V 37 37 36 36 3.3R 1 1 41 41 2.
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TAS5631B www.ti.com SLES263C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 GVDD (+12V) 1 PVDD 3.3R 1 VDD (+12V) 2 1000uF 63V 1 2 2 2 33nF 1 10uH GNDGND 1 2 1 2 2 1 12 2 2 2 1 1 1 1 2 1 3.3R GND 2 GND OUT_LEFT_M 3.3R 2 1 2 - GND 10k 1% 470uF 50V 1 + 100nF 63V 21 12 GND_D 470nF 250V 10k 10k 1% 1 2 PVDD 12 GND 33 OUT_LEFT_P 100nF 63V 1 34 2 R_COMP 2 35 35 1 2 2 GND GND 1 63V 10nF 10nF 63V 2 GND 1 2 1 2 GND 2 2.
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TAS5631B SLES263C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 www.ti.
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TAS5631B www.ti.com SLES263C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 THEORY OF OPERATION POWER SUPPLIES To facilitate system design, the TAS5631B needs only a 12-V supply in addition to the (typical) 50-V power-stage supply. An internal voltage regulator provides suitable voltage levels for the digital and low-voltage analog circuitry. Additionally, all circuitry requiring a floating voltage supply, e.g.
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TAS5631B SLES263C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 www.ti.com ERROR REPORTING The SD, OTW, OTW1, and OTW2 pins are active-low, open-drain outputs. Their function is for protection-mode signaling to a PWM controller or other system-control device. Any fault resulting in device shutdown is signaled by the SD pin going low. Likewise, OTW and OTW2 go low when the device junction temperature exceeds 125°C and OTW1 goes low when the junction temperature exceeds 100°C (see the following table).
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TAS5631B www.ti.com SLES263C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 PIN-TO-PIN SHORT-CIRCUIT PROTECTION (PPSC) The PPSC detection system protects the device from permanent damage if a power output pin (OUT_X) is shorted to GND_X or PVDD_X. For comparison, the OC protection system detects an overcurrent after the demodulation filter, whereas PPSC detects shorts directly at the pin before the filter. PPSC detection is performed at startup, i.e.
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TAS5631B SLES263C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 www.ti.com SYSTEM DESIGN CONSIDERATIONS A rising-edge transition on the reset input allows the device to execute the startup sequence and start switching. Apply only audio when the state of READY is high; that starts and stops the amplifier without having audible artifacts that are heard in the output transducers.
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TAS5631B www.ti.com SLES263C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 Note T1: PVDD decoupling bulk capacitors C60–C64 should be as close as possible to the PVDD and GND_X pins; the heat sink sets the distance. Wide traces should be routed on the top layer with direct connection to the pins and without going through vias. No vias or traces should be blocking the current path. Note T2: Close decoupling of PVDD with low-impedance X7R ceramic capacitors is placed under the heat sink and close to the pins.
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TAS5631B SLES263C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 www.ti.com Note B1: It is important to have a direct, low-impedance return path for high current back to the power supply. Keep impedance low from top to bottom side of PCB through a lot of ground vias. Note B2: Bootstrap low-impedance X7R ceramic capacitors placed on bottom side provide a short low-inductance current loop. Note B3: Return currents from bulk capacitors and output filter capacitors Figure 20.
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TAS5631B www.ti.com SLES263C – NOVEMBER 2010 – REVISED SEPTEMBER 2012 REVISION HISTORY Changes from Original (October 2010) to Revision A Page • Changed Title From: 600-W MONO To 400-W MONO ........................................................................................................ 1 • Changed Feature From: 600 W per Channel in Mono PBTL Configuration To: 400 W per Channel in Mono PBTL Configuration ..........................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) TAS5631BDKDR HSSOP DKD 44 500 330.0 24.4 TAS5631BPHDR HTQFP PHD 64 1000 330.0 24.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 14.7 16.4 4.0 20.0 24.0 Q1 17.0 17.0 1.5 20.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TAS5631BDKDR HSSOP DKD TAS5631BPHDR HTQFP PHD 44 500 367.0 367.0 45.0 64 1000 367.0 367.0 45.
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