TAS5711 www.ti.com SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010 20-W DIGITAL AUDIO-POWER AMPLIFIER WITH EQ, DRC, AND 2.1 MODE Check for Samples: TAS5711 FEATURES 1 • 2 • • Audio Input/Output – 20-W Into an 8-Ω Load From an 18-V Supply – Wide PVDD Range, From 8 V to 26 V – Efficient Class-D Operation Eliminates Need for Heatsinks – One Serial Audio Input (Two Audio Channels) – 2.1 Mode (2 SE + 1 BTL) – 2.
TAS5711 SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. SIMPLIFIED APPLICATION DIAGRAM 3.
TAS5711 www.ti.
TAS5711 SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010 www.ti.com FAULT Undervoltage Protection FAULT 4 4 Power On Reset Protection and I/O Logic AGND Temp.
R L Input Muxing Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): TAS5711 ½ 61 + 31 1BQ 21 (D8, D9) I2C:54 – V2IM + 2A 1BQ 5A 1BQ 1 1 + + 6BQ 5B 1BQ 32–36, 5C 6BQ 2B–2F, 58 55 + Vol1 + Auto-lp (0x46 Bit 5) 0 –1 + 5E 1BQ 1BQ 5D 1BQ 59 3D ealpha 3D ealpha Vol2 Vol2 ealpha 3A 3A ealpha Vol1 Energy MAXMUX R 1 + 2 I C Subaddress in Red Attack Decay Attack Decay Master ON/OFF (0x46[1]) Log Math Master ON/OFF (0x46[0]) Log Ma
TAS5711 SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010 www.ti.
TAS5711 www.ti.com SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010 PIN FUNCTIONS (continued) PIN NAME NO. TYPE (1) 5-V TOLERANT TERMINATION (2) DESCRIPTION DVSS 28 P Digital ground GND 29 P Analog ground for power stage 5, 32 P Gate drive internal regulator output. This pin must not be used to drive external devices.
TAS5711 SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010 www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) VALUE UNIT –0.3 to 3.6 V PVDD_x –0.3 to 30 V OC_ADJ –0.3 to 4.2 V –0.5 to DVDD + 0.5 V –0.5 to DVDD + 2.5 (3) V (3) V DVDD, AVDD Supply voltage 3.3-V digital input Input voltage 5-V tolerant (2) digital input (except MCLK) 5-V tolerant MCLK input –0.5 to AVDD + 2.
TAS5711 www.ti.com SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010 PWM OPERATION AT RECOMMENDED OPERATING CONDITIONS PARAMETER TEST CONDITIONS Output sample rate VALUE UNIT 11.025/22.05/44.1-kHz data rate ±2% 352.8 kHz 48/24/12/8/16/32-kHz data rate ±2% 384 PLL INPUT PARAMETERS AND EXTERNAL FILTER COMPONENTS PARAMETER fMCLKI tr / tf(MCLK) TEST CONDITIONS MIN MCLK Frequency 2.8224 MCLK duty cycle 40% TYP 50% MAX UNIT 24.
TAS5711 SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010 www.ti.com AC Characteristics (BTL) PVDD_x = 18 V, BTL AD mode, FS = 48 KHz, RL = 8 Ω, ROCP = 22 KΩ, CBST = 33 nF, audio frequency = 1 kHz, AES17 filter, fPWM = 384 kHz, TA = 25°C (unless otherwise specified). All performance is in accordance with recommended operating conditions (unless otherwise specified).
TAS5711 www.ti.com SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010 SERIAL AUDIO PORTS SLAVE MODE over recommended operating conditions (unless otherwise noted) TEST CONDITIONS PARAMETER MIN CL = 30 pF TYP 1.024 MAX UNIT 12.
TAS5711 SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010 www.ti.com I2C SERIAL CONTROL PORT OPERATION Timing characteristics for I2C Interface signals over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN No wait states MAX UNIT 400 kHz fSCL Frequency, SCL tw(H) Pulse duration, SCL high 0.6 tw(L) Pulse duration, SCL low 1.
TAS5711 www.ti.com SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010 RESET TIMING (RESET) Control signal parameters over recommended operating conditions (unless otherwise noted). Please refer to Recommended Use Model section on usage of all terminals. PARAMETER tw(RESET) Pulse duration, RESET active td(I2C_ready) Time to enable I2C MIN TYP MAX UNIT 12.0 ms 100 µs RESET tw(RESET) 2 2 I C Active I C Active td(I2C_ready) System Initialization. 2 Enable via I C.
TAS5711 SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010 www.ti.com TYPICAL CHARACTERISTICS, BTL CONFIGURATION TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 10 10 PVDD = 12V RL = 8Ω T A = 25°C PVDD = 8V RL = 8Ω T A = 25°C PO = 2.5W 0.1 0.1 PO = 0.5W PO = 1W 0.01 0.01 0.001 20 100 1k Frequency (Hz) 10k 10k 20k G002 Figure 7.
TAS5711 www.ti.com SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010 TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued) TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER 10 10 PVDD = 8V RL = 8Ω T A = 25°C PVDD = 12V RL = 8Ω T A = 25°C f = 20Hz 1 1 f = 1kHz THD+N (%) THD+N (%) f = 1kHz 0.1 0.01 f = 20Hz 0.1 0.01 f = 10kHz f = 10kHz 0.001 0.01 0.1 1 Output Power (W) 10 0.001 0.01 50 0.1 G005 1 Output Power (W) 50 G006 Figure 10.
TAS5711 SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010 www.ti.
TAS5711 www.ti.com SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010 TYPICAL CHARACTERISTICS, BTL CONFIGURATION (continued) CROSSTALK vs FREQUENCY CROSSTALK vs FREQUENCY 0 -10 -20 0 PO = 1W PVDD = 18V RL = 8Ω T A = 25°C -10 -20 -30 Crosstalk (dB) Crosstalk (dB) -30 PO = 1W PVDD = 24V RL = 8Ω T A = 25°C -40 -50 -60 -70 -40 -50 -60 Right to Left -70 Right to Left -80 -80 Left to Right -90 -90 Left to Right -100 20 100 1k Frequency (Hz) 10k 20k -100 20 G013 Figure 18.
TAS5711 SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010 www.ti.com TYPICAL CHARACTERISTICS, SE CONFIGURATION TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 10 10 PVDD = 12V RL = 4Ω T A = 25°C PVDD = 18V RL = 4Ω T A = 25°C 1 PO = 5W 1 PO = 2.5W THD+N (%) THD+N (%) PO = 2.5W 0.1 0.1 PO = 1W PO = 1W PO = 0.5W 0.01 0.001 20 0.01 100 1k Frequency (Hz) 10k 0.001 20 20k 100 G015 1k Frequency (Hz) 10k G016 Figure 20. Figure 21.
TAS5711 www.ti.com SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010 TYPICAL CHARACTERISTICS, SE CONFIGURATION (continued) OUTPUT POWER vs SUPPLY VOLTAGE EFFICIENCY vs TOTAL OUTPUT POWER 22 100 RL = 4Ω T A = 25°C 20 90 18 80 70 PVDD = 24V 14 12 Efficiency (%) Output Power (W) 16 THD+N = 10% 10 60 PVDD = 12V 50 40 8 30 6 THD+N = 1% 4 20 2 10 0 RL = 4Ω T A = 25°C 0 8 10 12 14 16 18 20 Supply Voltage (V) 22 24 26 0 G019 NOTE: Dashed lines represent thermally limited region.
TAS5711 SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010 www.ti.com TYPICAL CHARACTERISTICS, PBTL CONFIGURATION TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 10 10 PVDD = 12V RL = 4Ω T A = 25°C PVDD = 8V RL = 4Ω T A = 25°C 1 1 PO = 5W THD+N (%) THD+N (%) PO = 5W 0.1 PO = 1W 0.1 PO = 2W 0.01 0.01 PO = 2W PO = 1W 0.001 20 100 1k Frequency (Hz) 10k 0.
TAS5711 www.ti.com SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010 TYPICAL CHARACTERISTICS, PBTL CONFIGURATION (continued) TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER 10 10 PVDD = 8V RL = 4Ω T A = 25°C PVDD = 12V RL = 4Ω T A = 25°C 1 1 THD+N (%) THD+N (%) f = 20Hz 0.1 0.01 f = 20Hz 0.1 f = 10kHz 0.01 f = 1kHz f = 1kHz 0.001 0.01 0.1 f = 10kHz 1 Output Power (W) 10 0.001 0.01 50 1 Output Power (W) 10 50 G026 Figure 30.
TAS5711 SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010 www.ti.
TAS5711 www.ti.com SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010 DETAILED DESCRIPTION POWER SUPPLY To facilitate system design, the TAS5711 needs only a 3.3-V supply in addition to the (typical) 18-V power-stage supply. An internal voltage regulator provides suitable voltage levels for the gate drive circuitry. Additionally, all circuitry requiring a floating voltage supply, e.g., the high-side gate drive, is accommodated by built-in bootstrap circuitry requiring only a few external capacitors.
TAS5711 SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010 www.ti.com Table 1. FAULT Output States (continued) Power Stage Fault State FAULT NO-FAULT NO-FAULT FAULT Programmable Recovery Time ~300 ns T0450-01 Figure 36. Fault Timing Diagram DEVICE PROTECTION SYSTEM Overcurrent (OC) Protection With Current Limiting The device has independent, fast-reacting current detectors on all high-side and low-side power-stage FETs. The detector outputs are closely monitored by two protection systems.
TAS5711 www.ti.com SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010 CLOCK, AUTO DETECTION, AND PLL The TAS5711 is a slave device. It accepts MCLK, SCLK, and LRCLK. The digital audio processor (DAP) supports all the sample rates and MCLK rates that are defined in the clock control register . The TAS5711 checks to verify that SCLK is a specific value of 32 fS, 48 fS, or 64 fS. The DAP only supports a 1 × fS LRCLK. The timing relationship of these clocks to SDIN is shown in subsequent sections.
TAS5711 SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010 www.ti.com 2 2-Channel I S (Philips Format) Stereo Input 32 Clks LRCLK (Note Reversed Phase) 32 Clks Right Channel Left Channel SCLK SCLK MSB 24-Bit Mode 23 22 MSB LSB 9 8 5 4 5 4 1 0 1 0 1 0 LSB 23 22 9 8 5 4 19 18 5 4 1 0 15 14 1 0 1 0 20-Bit Mode 19 18 16-Bit Mode 15 14 T0034-01 NOTE: All data presented in 2s-complement form with MSB first. Figure 37.
TAS5711 www.ti.com SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010 2 2-Channel I S (Philips Format) Stereo Input LRCLK 16 Clks 16 Clks Left Channel Right Channel SCLK SCLK MSB 16-Bit Mode MSB LSB 15 14 13 12 11 10 9 5 8 4 3 2 1 0 LSB 15 14 13 12 11 10 9 5 8 4 3 2 1 T0266-01 NOTE: All data presented in 2s-complement form with MSB first. Figure 39.
TAS5711 SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010 www.ti.com 2-Channel Left-Justified Stereo Input (24-Bit Transfer Word Size) 24 Clks 24 Clks Left Channel Right Channel LRCLK SCLK SCLK MSB 24-Bit Mode 23 22 21 LSB 17 16 9 8 5 4 13 12 5 4 1 0 9 1 0 1 0 MSB LSB 21 17 16 9 8 5 4 19 18 17 13 12 5 4 1 0 15 14 13 9 1 0 23 22 1 0 20-Bit Mode 19 18 17 16-Bit Mode 15 14 13 8 8 T0092-02 NOTE: All data presented in 2s-complement form with MSB first. Figure 41.
TAS5711 www.ti.com SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010 it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 32, 48, or 64 × fS is used to clock in the data. The first bit of data appears on the data 8 bit-clock periods (for 24-bit data) after LRCLK toggles. In RJ mode the LSB of data is always clocked by the last bit clock before LRCLK transitions. The data is written MSB first and is valid on the rising edge of bit clock.
TAS5711 SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010 www.ti.com 2-Channel Right-Justified Stereo Input (24-Bit Transfer Word Size) 24 Clks 24 Clks Left Channel Right Channel LRCLK SCLK SCLK MSB 24-Bit Mode 23 22 LSB 19 18 15 14 6 5 2 1 0 19 18 15 14 6 5 2 1 0 15 14 6 5 2 1 0 LSB MSB 23 22 19 18 15 14 6 5 2 1 0 19 18 15 14 6 5 2 1 0 15 14 6 5 2 1 0 20-Bit Mode 16-Bit Mode T0092-03 Figure 44. Right Justified 48-fS Format Figure 45.
TAS5711 www.ti.com SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010 I2C SERIAL CONTROL INTERFACE The TAS5711 DAP has a bidirectional I2C interface that compatible with the I2C (Inter IC) bus protocol and supports both 100-kHz and 400-kHz data transfer rates for single and multiple byte write and read operations. This is a slave only device that does not support a multimaster bus environment or wait state insertion.
TAS5711 SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010 www.ti.com During multiple-byte read operations, the DAP responds with data, a byte at a time, starting at the subaddress assigned, as long as the master device continues to respond with acknowledges. If a particular subaddress does not contain 32 bits, the unused bits are read as logic 0. During multiple-byte write operations, the DAP compares the number of bytes transmitted to the number of bytes that are required for each specific subaddress.
TAS5711 www.ti.com SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010 Single-Byte Read As shown in Figure 49, a single-byte data read transfer begins with the master device transmitting a start condition followed by the I2C device address and the read/write bit. For the data read transfer, both a write followed by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal memory address to be read. As a result, the read/write bit becomes a 0.
TAS5711 SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010 www.ti.com Output Mode and MUX Selection 2.0 BTL AD Reg setting 0x20 (23) = 0 0x20 (19) = 0 0x05 (3) = X 0x05 (2) = 0 2.0 BTL BD Reg setting 0x20 (23) = 1 0x20 (19) = 1 0x05 (3) = X 0x05 (2) = 0 2.1 SE, BTL-AD Reg setting 0x20 (23) = 0 0x20 (19) = 0 0x05 (3) = 0 0x05 (2) = 1 2.
TAS5711 www.ti.com SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010 Dynamic Range Control (DRC) The DRC scheme has a single threshold, offset, and slope (all programmable). There is one ganged DRC for the left/right channels and one DRC for the subchannel. The DRC input/output diagram is shown in Figure 52. Refer to GDE software tool for more description on T, K, and O parameters.
TAS5711 SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010 www.ti.com BANK SWITCHING The TAS5711 uses an approach called bank switching together with automatic sample-rate detection. All processing features that must be changed for different sample rates are stored internally in three banks. The user can program which sample rates map to each bank. By default, bank 1 is used in 32kHz mode, bank 2 is used in 44.1/48 kHz mode, and bank 3 is used for all other rates.
TAS5711 www.ti.com SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010 The decimal value of a 3.23 format number can be found by following the weighting shown in Figure 54. If the most significant bit is logic 0, the number is a positive number, and the weighting shown yields the correct number. If the most significant bit is a logic 1, then the number is a negative number.
2 Submit Documentation Feedback Product Folder Link(s): TAS5711 PVDD RESET SCL SDA 0 ns 0 ns 100 ms 100 μs 3V 10 ms 8V 6V 13.5 ms Trim 50 ms DAP Config Other Config (1) tPLL has to be greater than 240 ms + 1.3 tstart. This constraint only applies to the first trim command following AVDD/DVDD power-up. It does not apply to trim commands following subsequent resets. (2) tstart/tstop = PWM start/stop time as defined in register 0X1A (3) When Mid-Z ramp is enabled (for 2.
TAS5711 www.ti.com SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010 3V AVDD/DVDD 0 ns 2 ms PDN 0 ns 2 I C 2 ms RESET 2 ms 0 ns 8V PVDD 6V T0420-05 Figure 58. Power Loss Sequence Recommended Command Sequences Initialization Sequence Use the following sequence to power-up and initialize the device: 1. Hold all digital inputs low and ramp up AVDD/DVDD to at least 3 V. 2.
TAS5711 SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010 www.ti.com Shutdown Sequence Enter: 1. Write 0x40 to register 0x05. 2. Wait at least 1 ms + 1.3 × tstop (where tstop is specified by register 0x1A). 3. If desired, reconfigure by returning to step 4 of initialization sequence. 1. Write 0x00 to register 0x05 (exit shutdown command may not be serviced for as much as 240 ms after trim following AVDD/DVDD powerup ramp). 2. Wait at least 1 ms + 1.
TAS5711 www.ti.com SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010 Table 4. Serial Control Interface Register Summary SUBADDRESS REGISTER NAME NO. OF BYTES INITIALIZATION VALUE CONTENTS A u indicates unused bits.
TAS5711 SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010 www.ti.com Table 4. Serial Control Interface Register Summary (continued) SUBADDRESS 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 42 REGISTER NAME ch1_bq[2] ch1_bq[3] ch1_bq[4] ch1_bq[5] ch1_bq[6] ch2_bq[0] ch2_bq[1] ch2_bq[2] ch2_bq[3] NO.
TAS5711 www.ti.com SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010 Table 4. Serial Control Interface Register Summary (continued) SUBADDRESS 0x34 0x35 0x36 REGISTER NAME ch2_bq[4] ch2_bq[5] ch2_bq[6] 0x37 - 0x39 0x3A DRC1 ae (3) NO.
TAS5711 SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010 www.ti.com Table 4. Serial Control Interface Register Summary (continued) SUBADDRESS 0x53 0x54 0x55 Ch 1 input mixer Ch 2 input mixer Channel 3 input mixer NO.
TAS5711 www.ti.com SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010 Table 4.
TAS5711 SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010 www.ti.com CLOCK CONTROL REGISTER (0x00) The clocks and data rates are automatically determined by the TAS5711. The clock control register contains the auto-detected clock status. Bits D7–D5 reflect the sample rate. Bits D4–D2 reflect the MCLK frequency. The device accepts a 64 fS or 32 fS SCLK rate for all MCLK ratios, but accepts a 48 fS SCLK rate for MCLK ratios of 192 fS and 384 fS only. Table 5.
TAS5711 www.ti.com SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010 ERROR STATUS REGISTER (0x02) The error bits are sticky and are not cleared by the hardware. This means that the software must clear the register (write zeroes) and then read them to determine if they are persistent errors. Error Definitions: • MCLK Error : MCLK frequency is changing. The number of MCLKs per LRCLK is changing. • SCLK Error: The number of SCLKs per LRCLK is changing. • LRCLK Error: LRCLK frequency is changing.
TAS5711 SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010 www.ti.com SERIAL DATA INTERFACE REGISTER (0x04) As shown in Table 9, the TAS5711 supports 9 serial data modes. The default is 24-bit, I2S mode, Table 9.
TAS5711 www.ti.com SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010 SYSTEM CONTROL REGISTER 2 (0x05) When bit D6 is set low, the system exits all channel shutdown and starts playing audio; otherwise, the outputs are shut down(hard mute). Table 10.
TAS5711 SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010 www.ti.com VOLUME REGISTERS (0x07, 0x08, 0x09, 0x0A) Step size is 0.5 dB. Master volume – 0x07 (default is mute) Channel-1 volume – 0x08 (default is 0 dB) Channel-2 volume – 0x09 (default is 0 dB) Channel-3 volume – 0x0A (default is 0 dB) Table 12.
TAS5711 www.ti.com SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010 MODULATION LIMIT REGISTER (0x10) The modulation limit is the maximum duty cycle of the PWM output waveform. Table 14. Modulation Limit Register (0x10) (1) D7 D6 D5 D4 D3 D2 D1 D0 MODULATION LIMIT – – – – – 0 0 0 99.2% – – – – – 0 0 1 – – – – – 0 1 0 – – – – – 0 1 1 96.9% – – – – – 1 0 0 96.1% – – – – – 1 0 1 95.3% – – – – – 1 1 0 94.5% – – – – – 1 1 1 93.
TAS5711 SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010 www.ti.com PWM SHUTDOWN GROUP REGISTER (0x19) Settings of this register determine which PWM channels are active. The value should be 0x30 for BTL mode and 0x3A for PBTL mode. The default value of this register is 0x30. The functionality of this register is tied to the state of bit D5 in the system control register. This register defines which channels belong to the shutdown group (SDG).
TAS5711 www.ti.com SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010 START/STOP PERIOD REGISTER (0x1A) This register is used to control the soft-start and soft-stop period following an enter/exit all channel shut down command or change in the PDN state. This helps reduce pops and clicks at start-up and shutdown.The times are only approximate and vary depending on device activity level and I2S clock stability. Table 17.
TAS5711 SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010 www.ti.com OSCILLATOR TRIM REGISTER (0x1B) The TAS5711 PWM processor contains an internal oscillator to support autodetect of I2S clock rates. This reduces system cost because an external reference is not required. Currently, TI recommends a reference resistor value of 18.2 kΩ (1%). This should be connected between OSC_RES and DVSSO. Writing 0x00 to register 0x1B enables the trim that was programmed at the factory.
TAS5711 www.ti.com SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010 INPUT MULTIPLEXER REGISTER (0x20) This register controls the modulation scheme (AD or BD mode) as well as the routing of I2S audio to the internal channels. Table 20.
TAS5711 SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010 www.ti.com CHANNEL 4 SOURCE SELECT REGISTER (0x21) This register selects the channel 4 source. Table 21.
TAS5711 www.ti.com SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010 Table 22.
TAS5711 SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010 www.ti.com BANK SWITCH AND EQ CONTROL (0x50) Table 24. Bank Switching Command D31 D30 D29 D28 D27 D26 D25 D24 0 – – – – – – – 32 kHz, does not use bank 3 1 – – – – – – – 32 kHz, uses bank 3 – 0 – – – – – – Reserved (1) – – 0 – – – – – Reserved (1) – – – 0 – – – – 44.1/48 kHz, does not use bank 3 – – – 1 – – – – 44.
TAS5711 www.ti.com SLOS600A – DECEMBER 2009 – REVISED AUGUST 2010 Table 24. Bank Switching Command (continued) D7 D6 D5 D4 D3 D2 D1 D0 1 – – – – – – – EQ OFF (bypass BQ 0-7 of channels 1 and 2) – 0 – – – – – – Reserved – – 0 – – – – – Ignore bank-mapping in bits D31–D8.Use default mapping. – – – 0 – – – – L and R can be written independently.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE MATERIALS INFORMATION www.ti.com 1-Aug-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device TAS5711PHPR Package Package Pins Type Drawing HTQFP PHP 48 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 16.4 Pack Materials-Page 1 9.6 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 9.6 1.5 12.0 16.
PACKAGE MATERIALS INFORMATION www.ti.com 1-Aug-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TAS5711PHPR HTQFP PHP 48 1000 336.6 336.6 31.
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