TAS5715 www.ti.com SLOS645 – AUGUST 2010 25-W DIGITAL AUDIO POWER AMPLIFIER WITH EQ AND DRC Check for Samples: TAS5715 FEATURES 1 • • • Audio Input/Output – 25-W Into an 8-Ω Load From an 18-V Supply – 50-W Support in PBTL Mode With 4-Ω Load – Wide PVDD Range, From 8 V to 26 V – Efficient Class-D Operation Eliminates Need for Heatsinks – Requires Only 3.
TAS5715 SLOS645 – AUGUST 2010 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. SIMPLIFIED APPLICATION DIAGRAM 3.
TAS5715 www.ti.
TAS5715 SLOS645 – AUGUST 2010 www.ti.com FAULT Undervoltage Protection FAULT 4 4 Power On Reset Protection and I/O Logic AGND Temp.
R L 0x77 0x76 0x73 0x72 + + 0x30–0x36 7BQ 0x29–0x2F 7BQ + Auto-lp (0x46 Bit 5) 0 –1 + 2 1BQ 5D 1BQ 59 I C Subaddress in Red 0x74 0x70 Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TAS5715 + + + + Volc config reg 0x0E Vol DRC Vol Vol2 DRC Vol1 0x52[0] 0x52[1] 0x51[0] 0x51[1] + + 2 I C:57 VDISTB 2 B0321-07 I C:56 VDISTA TAS5715 www.ti.
TAS5715 SLOS645 – AUGUST 2010 www.ti.
TAS5715 www.ti.com SLOS645 – AUGUST 2010 PIN FUNCTIONS (continued) PIN NAME NO.
TAS5715 SLOS645 – AUGUST 2010 www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) Supply voltage (1) VALUE UNIT DVDD, AVDD –0.3 to 3.6 V PVDD_x –0.3 to 30 V –0.5 to DVDD + 0.5 V –0.5 to DVDD + 2.5 (3) V (3) V 3.3-V digital input 5-V tolerant (2) digital input (except MCLK) Input voltage 5-V tolerant MCLK input –0.5 to AVDD + 2.
TAS5715 www.ti.com SLOS645 – AUGUST 2010 PLL INPUT PARAMETERS AND EXTERNAL FILTER COMPONENTS PARAMETER fMCLKI tr / tf(MCLK) TEST CONDITIONS MIN MCLK Frequency 2.8224 MCLK duty cycle 40% TYP 50% Rise/fall time for MCLK LRCLK allowable drift before LRCLK reset External PLL filter capacitor C1 SMD 0603 Y5V External PLL filter capacitor C2 External PLL filter resistor R MAX UNIT 12.288 MHz 60% 5 ns 4 MCLKs 47 nF SMD 0603 Y5V 4.
TAS5715 SLOS645 – AUGUST 2010 www.ti.com AC Characteristics (BTL, PBTL) PVDD_x = 18 V, BTL AD mode, fS = 48 KHz, RL = 8 Ω, ROCP = 22 KΩ, CBST = 33 nF, audio frequency = 1 kHz, AES17 filter, fPWM = 384 kHz, TA = 25°C (unless otherwise specified). All performance is in accordance with recommended operating conditions (unless otherwise specified). PARAMETER TEST CONDITIONS MIN 21.5 PVDD = 18 V, 7% THD, 1-kHz input signal 20.3 PVDD = 12 V, 10% THD, 1-kHz input signal 9.
TAS5715 www.ti.com SLOS645 – AUGUST 2010 SERIAL AUDIO PORTS SLAVE MODE over recommended operating conditions (unless otherwise noted) TEST CONDITIONS PARAMETER MIN CL = 30 pF TYP 1.024 MAX UNIT 3.
TAS5715 SLOS645 – AUGUST 2010 www.ti.com I2C SERIAL CONTROL PORT OPERATION Timing characteristics for I2C Interface signals over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN fSCL Frequency, SCL tw(H) Pulse duration, SCL high No wait states 0.6 tw(L) Pulse duration, SCL low 1.
TAS5715 www.ti.com SLOS645 – AUGUST 2010 RESET TIMING (RESET) Control signal parameters over recommended operating conditions (unless otherwise noted). Please refer to Recommended Use Model section on usage of all terminals. PARAMETER tw(RESET) MIN Pulse duration, RESET active TYP 2 td(I2C_ready) MAX UNIT 100 Time to enable I C ms 12.0 ms RESET tw(RESET) 2 2 I C Active I C Active td(I2C_ready) System Initialization. 2 Enable via I C.
TAS5715 SLOS645 – AUGUST 2010 www.ti.com TYPICAL CHARACTERISTICS, BTL CONFIGURATION, 8 Ω TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 10 10 PVDD = 8V RL = 8Ω T A = 25°C PVDD = 12V RL = 8Ω T A = 25°C 1 PO = 5W 1 PO = 2.5W THD+N (%) THD+N (%) PO = 2.5W 0.1 PO = 0.5W 0.1 PO = 1W PO = 1W 0.01 0.001 20 0.01 100 1k Frequency (Hz) 10k 0.
TAS5715 www.ti.com SLOS645 – AUGUST 2010 TYPICAL CHARACTERISTICS, BTL CONFIGURATION, 8 Ω (continued) TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER 10 10 PVDD = 8V RL = 8Ω T A = 25°C PVDD = 12V RL = 8Ω T A = 25°C 1 1 THD+N (%) THD+N (%) f = 20Hz 0.1 f = 1kHz 0.1 f = 1kHz 0.01 f = 20Hz 0.01 f = 10kHz f = 10kHz 0.001 0.01 0.1 1 Output Power (W) 10 0.001 0.01 40 0.1 G005 1 Output Power (W) 40 G006 Figure 10. Figure 11.
TAS5715 SLOS645 – AUGUST 2010 www.ti.com TYPICAL CHARACTERISTICS, BTL CONFIGURATION, 8 Ω (continued) OUTPUT POWER vs SUPPLY VOLTAGE EFFICIENCY vs TOTAL OUTPUT POWER 40 100 RL = 8Ω T A = 25°C 35 90 80 30 PVDD = 24V PVDD = 18V 25 Efficiency (%) Output Power (W) 70 THD+N = 10% 20 15 PVDD = 12V 50 PVDD = 8V 40 30 THD+N = 1% 10 60 20 5 RL = 8Ω T A = 25°C 10 0 0 8 10 12 14 16 18 20 Supply Voltage (V) 22 24 26 0 5 10 G009 NOTE: Dashed lines represent thermally limited region.
TAS5715 www.ti.com SLOS645 – AUGUST 2010 TYPICAL CHARACTERISTICS, BTL CONFIGURATION, 8 Ω (continued) CROSSTALK vs FREQUENCY CROSSTALK vs FREQUENCY 0 -10 -20 0 PO = 1W PVDD = 18V RL = 8Ω T A = 25°C -10 -20 -30 Crosstalk (dB) Crosstalk (dB) -30 PO = 1W PVDD = 24V RL = 8Ω T A = 25°C -40 -50 -60 -40 -50 -60 Right to Left -70 -70 Right to Left -80 -80 -90 -90 Left to Right Left to Right -100 20 100 1k Frequency (Hz) 10k 20k -100 20 G013 Figure 18.
TAS5715 SLOS645 – AUGUST 2010 www.ti.com TYPICAL CHARACTERISTICS, BTL CONFIGURATION, 4 Ω TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 10 10 PVDD = 12V RL = 4Ω T A = 25°C PVDD = 18V RL = 4Ω T A = 25°C PO = 5W 1 1 PO = 5W THD+N (%) THD+N (%) PO = 2.5W 0.1 PO = 1W PO = 1W 0.01 0.001 20 100 0.1 0.01 1k Frequency (Hz) 10k 0.001 20 20k 100 1k Frequency (Hz) G021 10k 20k G022 Figure 20. Figure 21.
TAS5715 www.ti.com SLOS645 – AUGUST 2010 TYPICAL CHARACTERISTICS, BTL CONFIGURATION, 4 Ω (continued) CROSSTALK vs FREQUENCY CROSSTALK vs FREQUENCY 0 -10 -10 -20 -30 -30 -40 -40 Crosstalk (dB) Crosstalk (dB) -20 0 PO = 1W PVDD = 12V RL = 4Ω T A = 25°C -50 -60 Right to Left -70 PO = 1W PVDD = 18V RL = 4Ω T A = 25°C -50 -60 Right to Left -70 -80 -80 Left to Right -90 -90 -100 -100 -110 20 100 1k Frequency (Hz) 10k 20k -110 20 G023 Figure 24.
TAS5715 SLOS645 – AUGUST 2010 www.ti.com TYPICAL CHARACTERISTICS, PBTL CONFIGURATION, 4 Ω TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 10 10 PVDD = 12V RL = 4Ω T A = 25°C PVDD = 24V RL = 4Ω T A = 25°C 1 1 PO = 2.5W PO = 5W THD+N (%) THD+N (%) PO = 5W 0.1 PO = 1W 0.01 0.001 20 100 PO = 2.5W 0.1 0.01 1k Frequency (Hz) 10k PO = 1W 0.001 20 20k 100 1k Frequency (Hz) G015 20k G016 Figure 26. Figure 27.
TAS5715 www.ti.com SLOS645 – AUGUST 2010 TYPICAL CHARACTERISTICS, PBTL CONFIGURATION, 4 Ω (continued) OUTPUT POWER vs SUPPLY VOLTAGE EFFICIENCY vs TOTAL OUTPUT POWER 100 60 RL = 4Ω T A = 25°C 90 50 80 PVDD = 24V 70 40 PVDD = 12V Efficiency (%) Output Power (W) THD+N = 10% 30 THD+N = 1% 20 60 50 40 30 20 10 RL = 4Ω T A = 25°C 10 0 0 8 10 12 14 16 18 20 Supply Voltage (V) 22 24 26 0 G019 NOTE: Dashed lines represent thermally limited region. Figure 30.
TAS5715 SLOS645 – AUGUST 2010 www.ti.com DETAILED DESCRIPTION POWER SUPPLY To facilitate system design, the TAS5715 needs only a 3.3-V supply in addition to the (typical) 18-V power-stage supply. An internal voltage regulator provides suitable voltage levels for the gate drive circuitry. Additionally, all circuitry requiring a floating voltage supply, e.g., the high-side gate drive, is accommodated by built-in bootstrap circuitry requiring only a few external capacitors.
TAS5715 www.ti.com SLOS645 – AUGUST 2010 overloaded, a second protection system triggers a latching shutdown, resulting in the power stage being set in the high-impedance (Hi-Z) state. The device returns to normal operation once the fault condition (i.e., a short circuit on the output) is removed. Current limiting and overcurrent protection are not independent for half-bridges.
TAS5715 SLOS645 – AUGUST 2010 www.ti.com PWM Section The TAS5715 DAP device uses noise-shaping and sophisticated nonlinear correction algorithms to achieve high power efficiency and high-performance digital audio reproduction. The DAP uses a fourth-order noise shaper to increase dynamic range and SNR in the audio band. The PWM section accepts 24-bit PCM data from the DAP and outputs two BTL PWM audio output channels.
TAS5715 www.ti.com SLOS645 – AUGUST 2010 2 2-Channel I S (Philips Format) Stereo Input 32 Clks LRCLK (Note Reversed Phase) 32 Clks Right Channel Left Channel SCLK SCLK MSB 24-Bit Mode 23 22 MSB LSB 9 8 5 4 5 4 1 0 1 0 1 0 LSB 23 22 9 8 5 4 19 18 5 4 1 0 15 14 1 0 1 0 20-Bit Mode 19 18 16-Bit Mode 15 14 T0034-01 NOTE: All data presented in 2s-complement form with MSB first. Figure 32.
TAS5715 SLOS645 – AUGUST 2010 www.ti.com 2 2-Channel I S (Philips Format) Stereo Input LRCLK 16 Clks 16 Clks Left Channel Right Channel SCLK SCLK MSB 16-Bit Mode MSB LSB 15 14 13 12 11 10 9 5 8 4 3 2 1 0 LSB 15 14 13 12 11 10 9 5 8 4 3 2 1 T0266-01 NOTE: All data presented in 2s-complement form with MSB first. Figure 34.
TAS5715 www.ti.com SLOS645 – AUGUST 2010 2-Channel Left-Justified Stereo Input (24-Bit Transfer Word Size) 24 Clks 24 Clks Left Channel Right Channel LRCLK SCLK SCLK MSB 24-Bit Mode 23 22 21 LSB 17 16 9 8 5 4 13 12 5 4 1 0 9 1 0 1 0 MSB LSB 21 17 16 9 8 5 4 19 18 17 13 12 5 4 1 0 15 14 13 9 1 0 23 22 1 0 20-Bit Mode 19 18 17 16-Bit Mode 15 14 13 8 8 T0092-02 NOTE: All data presented in 2s-complement form with MSB first. Figure 36.
TAS5715 SLOS645 – AUGUST 2010 www.ti.com it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at 32, 48, or 64 × fS is used to clock in the data. The first bit of data appears on the data 8 bit-clock periods (for 24-bit data) after LRCLK toggles. In RJ mode the LSB of data is always clocked by the last bit clock before LRCLK transitions. The data is written MSB-first and is valid on the rising edge of bit clock.
TAS5715 www.ti.com SLOS645 – AUGUST 2010 2-Channel Right-Justified Stereo Input (24-Bit Transfer Word Size) 24 Clks 24 Clks Left Channel Right Channel LRCLK SCLK SCLK MSB 24-Bit Mode 23 22 LSB 19 18 15 14 6 5 2 1 0 19 18 15 14 6 5 2 1 0 15 14 6 5 2 1 0 LSB MSB 23 22 19 18 15 14 6 5 2 1 0 19 18 15 14 6 5 2 1 0 15 14 6 5 2 1 0 20-Bit Mode 16-Bit Mode T0092-03 Figure 39. Right-Justified 48-fS Format Figure 40.
TAS5715 SLOS645 – AUGUST 2010 www.ti.com I2C SERIAL CONTROL INTERFACE The TAS5715 DAP has a bidirectional I2C interface that is compatible with the Inter IC (I2C) bus protocol and supports both 100-kHz and 400-kHz data transfer rates for single- and multiple-yte write and read operations. This is a slave-only device that does not support a multimaster bus environment or wait-state insertion. The control interface is used to program the registers of the device and to read device status.
TAS5715 www.ti.com SLOS645 – AUGUST 2010 Supplying a subaddress for each subaddress transaction is referred to as random I2C addressing. The TAS5715 also supports sequential I2C addressing. For write transactions, if a subaddress is issued followed by data for that subaddress and the 15 subaddresses that follow, a sequential I2C write transaction has taken place, and the data for all 16 subaddresses is successfully received by the TAS5715.
TAS5715 SLOS645 – AUGUST 2010 www.ti.com Single-Byte Read As shown in Figure 44, a single-byte data-read transfer begins with the master device transmitting a start condition followed by the I2C device address and the read/write bit. For the data-read transfer, both a write followed by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal memory address to be read. As a result, the read/write bit becomes a 0.
TAS5715 www.ti.com SLOS645 – AUGUST 2010 Bit 0: This is bit should be 1 if the headphone function is used in the TAS5715. If the headphone is not used, this bit can be cleared to 0. Then if bit 1 is also set to 1, the TAS5715 drives the FAULTZ signal out on the A_SEL pin. FAULTZ is the internal power-stage fault signal asserted low during errors like overcurrent, overtemperature, and UVP. Figure 46 shows the connection of A_SEL_HP_SDZ pin to headphone shutdown.
TAS5715 SLOS645 – AUGUST 2010 www.ti.com PWM DC Detection The TAS5715 supports a PWM dc-detect function. This is to detect dc present in the input source and generated by another means in the blocks prior to PCM-to-PWM conversion. If enabled (0x46, bit 10), the detection block checks for PWM duty cycle. If it is above the programmed threshold (0x0F, bits 7–4]) for more than the programmed duration of time (0x0F, bits 3–0), the PWM dc error flag is set on error register 0x02, bit 0.
TAS5715 www.ti.com SLOS645 – AUGUST 2010 Automatic Gain Limit (DRC) The DRC scheme has a single programmable threshold. There is one ganged DRC for the high-band left/right channels and one DRC for the low-band left/right channels. Output Level (dB) The DRC input/output diagram is shown in Figure 48. 1:1 Transfer Function Implemented Transfer Function T Input Level (dB) M0176-01 Professional-quality dynamic range compression automatically adjusts volume to flatten volume level.
TAS5715 SLOS645 – AUGUST 2010 www.ti.com Attack and release events occur only when level remains above or below the threshold continuously during the time-constant time. And the constant time is controlled by the attack/release rate. If the attack/release rate is short, DRC operates frequently. Attack time defines how fast to cut the signal to bring it under the threshold. Similarly, release time defines how fast to release the cut back to normal. Attack and release are shown in Figure 50.
TAS5715 www.ti.com SLOS645 – AUGUST 2010 HPF L_IN DRC-1 Speaker EQ L_OUT LPF DRC-2 B0425-01 Figure 51. Two-Band DRC A crossover biquad should be used only for two-band DRC. It should be all-pass for the one-band DRC mode. Only DRC1 (upper band) is used in the one-band DRC mode.
TAS5715 SLOS645 – AUGUST 2010 www.ti.com BANK SWITCHING The TAS5715 uses an approach called bank switching together with automatic sample-rate detection. All processing features that must be changed for different sample rates are stored internally in three banks. The user can program which sample rates map to each bank. By default, bank 1 is used in 32-kHz mode, bank 2 is used in 44.1/48-kHz mode, and bank 3 is used for all other rates.
TAS5715 www.ti.com SLOS645 – AUGUST 2010 The decimal value of a 3.23 format number can be found by following the weighting shown in Figure 52. If the most significant bit is logic 0, the number is a positive number, and the weighting shown yields the correct number. If the most significant bit is a logic 1, then the number is a negative number. In this case every bit must be inverted, a 1 added to the result, and then the weighting shown in Figure 53 applied to obtain the magnitude of the negative number.
2 Submit Documentation Feedback Product Folder Link(s): TAS5715 PVDD RESET SCL SDA 0 ns 0 ns 100 ms 100 μs 3V 10 ms 8V 6V 13.5 ms Trim 50 ms DAP Config Other Config tPLL (1) tPLL has to be greater than 240 ms + 1.3 tstart. This constraint only applies to the first trim command following AVDD/DVDD power-up. It does not apply to trim commands following subsequent resets.
TAS5715 www.ti.com SLOS645 – AUGUST 2010 3V AVDD/DVDD 0 ns 2 ms PDN 0 ns 2 I C 2 ms RESET 2 ms 0 ns 8V PVDD 6V T0420-05 Figure 56. Power Loss Sequence Initialization Sequence Use the following sequence to power-up and initialize the device: 1. Hold all digital inputs low and ramp up AVDD/DVDD to at least 3V. 2. Initialize digital inputs and PVDD supply as follows: • Drive RESET = 0, PDN = 1, and other digital inputs to their desired state while ensuring that all are never more than 2.
TAS5715 SLOS645 – AUGUST 2010 www.ti.com Shutdown Sequence Enter: 1. Ensure I2S clocks have been stable and valid for at least 50ms. 2. Write 0x40 to register 0x05. 3. Wait at least 1ms+1.3*Tstop (where Tstop is specified by register 0x1A). 4. Once in shutdown, stable clocks are not required while device remains idle. 5. If desired, reconfigure by ensuring that clocks have been stable and valid for at least 50ms before returning to step 4 of initialization sequence. 1.
TAS5715 www.ti.com SLOS645 – AUGUST 2010 Headphone Usage HP/SPKR (SE/BTL) VALID PWM_A(L+) PWM_C(R+) SpkrL+/R+ 50% t(exitSDHP) t(mute) PWM_B(L–) PWM_D(R–) SpkrL+/R+ HPL/R t(enterSDHPamp) t(mute) t(exitSDHPamp) SpkrL–/R– SpkrL–/R– 50% t(enterSD) t(exitSD) FAULT = 1 Output HPSD (A0/FAULT) Hi-Z (Ext.
TAS5715 SLOS645 – AUGUST 2010 www.ti.
TAS5715 www.ti.com SLOS645 – AUGUST 2010 Headphone-Mode All-Channel Shutdown HP/SPKR (SE/BTL) VALID PWM_A(L+) PWM_C(R+) HPL/R HPL/R t(exitSDHP) t(mute) t(enterSDHPamp) t(exitSDHPamp) PWM_B(L–) PWM_D(R–) FAULT = 1 Output HPSD (A0/FAULT) Hi-Z (Ext. Pulldown) I2C: SCL SDA Mute Disable FAULT Enter ACSD HP Config Exit ACSD Enable FAULT Unmute PDN T0454-01 PARAMETE R t(mute) t(exitSDHP) t(exitSDHPamp) t(enterSDHPamp) DESCRIPTION MIN MAX UNIT 5 + 1.3 × t(volramp) ms 1 + 1.
TAS5715 SLOS645 – AUGUST 2010 • • • • • • • 46 www.ti.com Write to register 0xC9 with a value of 0x000600EA. Write to register 0xCA with a value of 0x0000000000000098. Note that register 0xCA is a write-only register. Reads from this register are prohibited. Write to register 0x03 with a value of 0x88. Write to register 0x00 with a value of 0x6D. Write to register 0x00 with a value of 0x6C. Write to register 0x03 with a value of 0x80. Write to register 0x05 with a value of 0x00.
TAS5715 www.ti.com SLOS645 – AUGUST 2010 Table 3. Serial Control Interface Register Summary SUBADDRESS REGISTER NAME NO. OF BYTES INITIALIZATION VALUE CONTENTS A u indicates unused bits.
TAS5715 SLOS645 – AUGUST 2010 www.ti.com Table 3. Serial Control Interface Register Summary (continued) SUBADDRESS 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 48 REGISTER NAME ch1_bq[2] ch1_bq[3] ch1_bq[4] ch1_bq[5] ch1_bq[6] ch2_bq[0] ch2_bq[1] ch2_bq[2] ch2_bq[3] NO.
TAS5715 www.ti.com SLOS645 – AUGUST 2010 Table 3. Serial Control Interface Register Summary (continued) SUBADDRESS 0x34 0x35 0x36 REGISTER NAME ch2_bq[4] ch2_bq[5] ch2_bq[6] NO.
TAS5715 SLOS645 – AUGUST 2010 www.ti.com Table 3. Serial Control Interface Register Summary (continued) SUBADDRESS REGISTER NAME NO. OF BYTES CONTENTS 0x54 Ch 2 input mixers 16 Channel-2 input mixers can be accessed using I2C subaddresses 0x74–0x77 using 4-byte access 0x56 Output post-scale 4 u[31:26], post[25:0] 0x0080 0000 0x57 Output pre-scale 4 u[31:26], pre[25:0] (9.
TAS5715 www.ti.com SLOS645 – AUGUST 2010 CLOCK CONTROL REGISTER (0x00) The clocks and data rates are automatically determined by the TAS5715. The clock control register contains the auto-detected clock status. Bits D7–D5 reflect the sample rate. Bits D4–D2 reflect the MCLK frequency. Table 4.
TAS5715 SLOS645 – AUGUST 2010 www.ti.com ERROR STATUS REGISTER (0x02) The error bits are sticky and are not cleared by the hardware. This means that the software must clear the register (write zeroes) and then read them to determine if they are persistent errors. Error definitions: • MCLK error : MCLK frequency is changing. The number of MCLKs per LRCLK is changing. • SCLK error: The number of SCLKs per LRCLK is changing. • LRCLK error: LRCLK frequency is changing.
TAS5715 www.ti.com SLOS645 – AUGUST 2010 Table 7.
TAS5715 SLOS645 – AUGUST 2010 www.ti.com SYSTEM CONTROL REGISTER 2 (0x05) When bit D6 is set low, the system exits all-channel shutdown and starts playing audio; otherwise, the outputs are shut down (hard mute). Table 9.
TAS5715 www.ti.com SLOS645 – AUGUST 2010 VOLUME REGISTERS (0x07, 0x08, 0x09, 0x0C) Step size is 0.5 dB. Master volume – 0x07 (default is mute) Channel-1 volume – 0x08 (default is 0 dB) Channel-2 volume – 0x09 (default is 0 dB) Headphone volume – 0x0C (default is 0 dB) Volume in the TAS5715 is not intended for dynamic changes. Channel volumes are set during initialization. Master volume is written with a value 0xFF to MUTE and with a value of 0x30 to UNMUTE during normal mode.
TAS5715 SLOS645 – AUGUST 2010 www.ti.com Table 12. Master Volume Table (continued) 56 HEX dB HEX dB HEX dB HEX dB HEX dB 11 15.5 41 –8.5 71 –32.5 A1 –56.5 D1 –80.5 12 15 42 –9 72 –33 A2 –57 D2 –81 13 14.5 43 –9.5 73 –33.5 A3 –57.5 D3 –81.5 14 14 44 –10 74 –34 A4 –58 D4 –82 15 13.5 45 –10.5 75 –34.5 A5 –58.5 D5 –82.5 16 13 46 –11 76 –35 A6 –59 D6 –83 17 12.5 37 –11.5 77 –35.5 A7 –59.5 D7 –83.
TAS5715 www.ti.com SLOS645 – AUGUST 2010 VOLUME CONFIGURATION REGISTER (0x0E) Bits D2–D0: Volume slew rate (Used to control volume change and MUTE ramp rates). These bits control the number of steps in a volume ramp. Volume steps occur at a rate that depends on the sample rate of the I2S data as follows: Sample rate (KHz) Approximate ramp rate 8/16/32 125 ms/step 11.025/22.05/44.1 90.7 ms/step 12/24/48 83.3 ms/step Table 13.
TAS5715 SLOS645 – AUGUST 2010 www.ti.com Table 14. DC Detect Control Register (0x0F)(1) (continued) 58 D7 D6 D5 D4 D3 D2 D1 D0 – – – – 0 1 1 1 1256.8 – – – – 1 0 0 0 1413.9 – – – – 1 0 0 1 1571 – – – – 1 0 1 0 1728.1 – – – – 1 0 1 1 1885.2 – – – – 1 1 0 0 2042.3 – – – – 1 1 0 1 2199.4 – – – – 1 1 1 0 2356.5 – – – – 1 1 1 1 2513.
TAS5715 www.ti.com SLOS645 – AUGUST 2010 MODULATION LIMIT REGISTER (0x10) Table 15. Modulation Limit Register (0x10) (1) D7 D6 D5 D4 D3 D2 D1 D0 MODULATION LIMIT 0 0 0 0 0 – – – Reserved – – – – – 0 0 0 99.2% – – – – – 0 0 1 – – – – – 0 1 0 97.7% – – – – – 0 1 1 96.9% – – – – – 1 0 0 96.1% – – – – – 1 0 1 95.3% – – – – – 1 1 0 94.5% – – – – – 1 1 1 93.8% 98.4% (1) Default values are in bold.
TAS5715 SLOS645 – AUGUST 2010 www.ti.com PWM SHUTDOWN GROUP REGISTER (0x19) Settings of this register determine which PWM channels are active. The value should be 0x30 for BTL mode and 0x3A for PBTL mode. The default value of this register is 0x30. The functionality of this register is tied to the state of bit D5 in the system control register. This register defines which channels belong to the shutdown group (SDG).
TAS5715 www.ti.com SLOS645 – AUGUST 2010 START/STOP PERIOD REGISTER (0x1A) This register is used to control the soft-start and soft-stop period following an enter/exit all-channel shutdown command or change in the PDN state. This helps reduce pops and clicks at start-up and shutdown.The times are only approximate and vary depending on device activity level and I2S clock stability. Table 18.
TAS5715 SLOS645 – AUGUST 2010 www.ti.com OSCILLATOR TRIM REGISTER (0x1B) The TAS5715 PWM processor contains an internal oscillator to support autodetect of I2S clock rates. This reduces system cost because an external reference is not required. Currently, TI recommends a reference resistor value of 18.2 kΩ (1%). This should be connected between OSC_RES and DVSSO. Writing 0x00 to reg 0x1B enables the trim that was programmed at the factory. Note that trim must always be run following reset of the device.
TAS5715 www.ti.com SLOS645 – AUGUST 2010 INPUT MULTIPLEXER REGISTER (0x20) This register controls the modulation scheme (AD or BD mode) as well as the routing of I2S audio to the internal channels. Table 21.
TAS5715 SLOS645 – AUGUST 2010 www.ti.com RESERVED (0x21–0x24) PWM OUTPUT MUX REGISTER (0x25) This DAP output mux selects which internal PWM channel is output to the external pins. Any channel can be output to any external output pin.
TAS5715 www.ti.com SLOS645 – AUGUST 2010 DRC AND DC DETECT CONTROL (0x46) Table 23.
TAS5715 SLOS645 – AUGUST 2010 www.ti.com BANK SWITCH AND EQ CONTROL (0x50) Table 24. Bank Switching Command D31 D30 D29 D28 D27 D26 D25 D24 0 – – – – – – – 32 kHz, does not use bank 3 1 – – – – – – – 32 kHz, uses bank 3 – 0 – – – – – – Reserved – – 0 – – – – – Reserved – – – 0 – – – – 44.1/48 kHz, does not use bank 3 – – – 1 – – – – 44.
TAS5715 www.ti.com SLOS645 – AUGUST 2010 Table 24. Bank Switching Command (continued) D7 D6 D5 D4 D3 D2 D1 D0 1 – – – – – – – EQ OFF (bypass BQ 0–7 of channels 1 and 2) – 0 – – – – – – Reserved – – 0 – – – – – Ignore bank-mapping in bits D31–D8.Use default mapping. – – – 0 – – – – L and R can be written independently. – – – 1 – – – – L and R are ganged for EQ biquads; a write to the left-channel biquad is also written to the right-channel biquad.
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PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device TAS5715PHPR Package Package Pins Type Drawing HTQFP PHP 48 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 16.4 Pack Materials-Page 1 9.6 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 9.6 1.5 12.0 16.
PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TAS5715PHPR HTQFP PHP 48 1000 336.6 336.6 31.
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