Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLinear ICsLinear IC - Audio amplifier 2-channel (stereo) with stereo headphones Class D HTQFP 48 (7x

TAS5717

TAS5719

www.ti.com

SLOS655A –NOVEMBER 2010–REVISED FEBRUARY 2011

10-W/15-W Digital Audio Power Amplifier with Integrated Cap-Free HP Amplifier

Check for Samples: TAS5717, TAS5719

FEATURES

• Audio Input/Output

• Benefits

– TAS5717 Supports 2×10 W and TAS5719 – EQ: Speaker Equalization Improves Audio

Supports 2×15 W Output Performance

– Wide PVDD Range, From 4.5 V to 26 V – DRC: Dynamic Range Compression. Can

Be Used As Power Limiter. Enables

– Efficient Class-D Operation Eliminates

Speaker Protection, Easy Listening,

Need for Heatsinks

Night-Mode Listening

– Requires Only 3.3 V and PVDD

– DirectPath Technology: Eliminates Bulky

– One Serial Audio Input (Two Audio

DC Blocking Capacitors

Channels)

– Stereo Headphone/Stereo Line Drivers:

– I

C Address Selection via PIN (Chip Select)

Adjust Gain via External Resistors,

– Supports 8-kHz to 48-kHz Sample Rate

Dedicated Active Headpone Mute Pin, High

(LJ/RJ/I

Signal-to-Noise Ratio

– External Headphone-Amplifier Shutdown

– Two-Band DRC: Set Two Different

Signal

Thresholds for Low- and High-Frequency

– Integrated CAP-Free Headphone Amplifier

Content

– Stereo Headphone (Stereo 2-V RMS Line

Driver) Outputs DESCRIPTION

• Audio/PWM Processing

The TAS5717/TAS5719 is a 10-W/15-W, efficient,

digital audio-power amplifier for driving stereo

– Independent Channel Volume Controls With

bridge-tied speakers. One serial data input allows

24-dB to Mute

processing of up to two discrete audio channels and

– Programmable Two-Band Dynamic Range

seamless integration to most digital audio processors

Control

and MPEG decoders. The device accepts a wide

– 14 Programmable Biquads for Speaker EQ

range of input data and data rates. A fully

programmable data path routes these channels to the

– Programmable Coefficients for DRC Filters

internal speaker drivers.

– DC Blocking Filters

The TAS5717/9 is a slave-only device receiving all

– 0.125-dB Fine Volume Support

clocks from external sources. The TAS5717/TAS5719

• General Features

operates with a PWM carrier between a 384-kHz

– Serial Control Interface Operational Without

switching rate and a 352-KHz switching rate,

MCLK

depending on the input sample rate. Oversampling

combined with a fourth-order noise shaper provides a

– Factory-Trimmed Internal Oscillator for

flat noise floor and excellent dynamic range from

Automatic Rate Detection

20 Hz to 20 kHz.

– Surface Mount, 48-Pin, 7-mm × 7-mm

HTQFP Package

– AD, BD, and Ternary PWM-Mode Support

– Thermal and Short-Circuit Protection

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2FilterPro is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (68 pages)

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TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com 10-W/15-W Digital Audio Power Amplifier with Integrated Cap-Free HP Amplifier Check for Samples: TAS5717, TAS5719 FEATURES 1 • 2 • • Audio Input/Output – TAS5717 Supports 2×10 W and TAS5719 Supports 2×15 W Output – Wide PVDD Range, From 4.5 V to 26 V – Efficient Class-D Operation Eliminates Need for Heatsinks – Requires Only 3.
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TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. SIMPLIFIED APPLICATION DIAGRAM 3.3 V 4.
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TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.
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R L 1BQ 30 1BQ 26 0x77 0x76 0x73 0x72 9BQ 31–39 9BQ 27–2F Submit Documentation Feedback Product Folder Link(s): TAS5717 TAS5719 2BQ 5A, 5B 2BQ 5E, 5F 2BQ 5C, 5D 2BQ 58, 59 0x75 0x74 v2im1 0x71 0x70 2 Vol Vol Vol2 Vol1 0x46[1] 0x46[0] Vol Config Reg 0x0E AGL AGL I C Subaddress in Red 0x52[0] 0x52[1] 0x51[0] 0x51[1] 2 2 32 Level Meter clip24 clip24 2 I C:0x6B (32Bit-Left Level) 32 32 32 I C:0x6C (32 Bit-Right Level) I C:57 VDISTB 2 I C:56 VDISTA B032
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TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.
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TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com PIN FUNCTIONS (continued) PIN NAME NO.
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TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) Supply voltage Input voltage VALUE UNIT DVDD, AVDD, HPVDD –0.3 to 3.6 V PVDD_X –0.3 to 30 V HPL_IN, HPR_IN –0.3 to 4.2 V 3.3-V digital input –0.5 to DVDD + 0.5 V (3) V –0.5 to AVDD + 2.
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TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com RECOMMENDED OPERATING CONDITIONS MIN NOM MAX 3 3.3 3.6 UNIT Digital/analog supply voltage DVDD, AVDD Half-bridge supply voltage PVDD_X VIH High-level input voltage 5-V tolerant VIL Low-level input voltage 5-V tolerant 0.
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TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com ELECTRICAL CHARACTERISTICS DC Characteristics TA = 25°, PVCC_X = 13 V, DVDD = AVDD = 3.3 V, RL= 8 Ω, BTL AD Mode, fS = 48 KHz (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX VOH High-level output voltage FAULTZ and SDA IOH = –4 mA DVDD = 3 V VOL Low-level output voltage FAULTZ and SDA IOL = 4 mA DVDD = 3 V 0.5 IIL Low-level input current VI < VIL ; DVDD = AVDD = 3.
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TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com AC Characteristics (BTL) PVDD_X = 12 V, BTL AD mode, fS = 48 KHz, RL = 8 Ω, audio frequency = 1 kHz, (unless otherwise noted). All performance is in accordance with recommended operating conditions, unless otherwise specified. PARAMETER PO TEST CONDITIONS Power output per channel MIN 10 PVDD = 8 V, 10% THD, 1-kHz input signal 4.
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TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com SERIAL AUDIO PORTS SLAVE MODE over recommended operating conditions (unless otherwise noted) TEST CONDITIONS PARAMETER MIN TYP MAX UNIT 12.288 MHz fSCLKIN Frequency, SCLK 32 × fS, 48 × fS, 64 × fS tsu1 Setup time, LRCLK to SCLK rising edge 10 ns th1 Hold time, LRCLK from SCLK rising edge 10 ns tsu2 Setup time, SDIN to SCLK rising edge 10 ns th2 Hold time, SDIN from SCLK rising edge 10 CL = 30 pF 1.
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TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com I2C SERIAL CONTROL PORT OPERATION Timing characteristics for I2C Interface signals over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN fSCL Frequency, SCL tw(H) Pulse duration, SCL high No wait states 0.6 tw(L) Pulse duration, SCL low 1.
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TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com RESET TIMING (RESET) Control signal parameters over recommended operating conditions (unless otherwise noted). Please refer to Recommended Use Model section on usage of all terminals. PARAMETER tw(RESET) MIN Pulse duration, RESET active TYP 2 td(I2C_ready) MAX UNIT μs 100 Time to enable I C 12 ms RESET tw(RESET) 2 2 I C Active I C Active td(I2C_ready) System Initialization. 2 Enable via I C. T0421-01 NOTES: 1.
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TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com TYPICAL CHARACTERISTICS, BTL CONFIGURATION, 8Ω SPACER SPACER TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY SPACER SPACER TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 10 10 PVDD = 8V RL = 8Ω TA = 25°C PVDD = 12V RL = 8Ω TA = 25°C 1 THD+N (%) THD+N (%) 1 0.1 0.01 0.1 0.01 PO = 1W PO = 2.5W PO = 5W 0.001 20 100 PO = 1W PO = 2.5W PO = 5W 1k Frequency (Hz) 10k 0.
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TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com TYPICAL CHARACTERISTICS, BTL CONFIGURATION, 8Ω (continued) SPACER SPACER TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER SPACER SPACER TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER 10 10 PVDD = 8V RL = 8Ω TA = 25°C PVDD = 12V RL = 8Ω TA = 25°C 1 THD+N (%) THD+N (%) 1 0.1 0.01 0.1 0.01 f = 20Hz f = 1kHz 0.001 0.01 0.1 1 Output Power (W) 10 f = 20Hz f = 1kHz 0.001 0.01 40 1 Output Power (W) 10 Figure 9.
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TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.
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TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.
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TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com TYPICAL CHARACTERISTICS, HEADPHONE TESTS, SE CONFIGURATION, 32Ω SPACER ANALOG IN TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY SPACER PWM IN TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 10 10 HPVDD = 3.3V RL = 32Ω TA = 25°C HPVDD = 3.3V RL = 32Ω TA = 25°C 1 THD+N (%) THD+N (%) 1 0.1 0.01 0.1 0.01 PO = 10mW 0.001 20 100 PO = 10mW 1k Frequency (Hz) 10k 20k 0.001 20 Figure 21.
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TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com TYPICAL CHARACTERISTICS, LINE DRIVER TESTS, SE CONFIGURATION, 5kΩ SPACER ANALOG IN TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY SPACER PWM IN TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT VOLTAGE 10 10 HPVDD = 3.3V RL = 5kΩ TA = 25°C PVDD =3.3V RL = 5kΩ TA = 25°C 1 THD+N (%) THD+N (%) 1 0.1 0.1 0.01 0.01 VO = 1Vrms 0.001 20 100 f = 1kHz 1k Frequency (Hz) 10k 20k 0.001 10m 100m Output Voltage (V) Figure 23.
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TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com DETAILED DESCRIPTION POWER SUPPLY To facilitate system design, the TAS5717/9 needs only a 3.3-V supply in addition to the (typical) 13-V power-stage supply. An internal voltage regulator provides suitable voltage levels for the gate drive circuitry. Additionally, all circuitry requiring a floating voltage supply, e.g.
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TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com Undervoltage Protection (UVP) and Power-On Reset (POR) The UVP and POR circuits of the TAS5717/9 fully protect the device in any power-up/down and brownout situation. While powering up, the POR circuit resets the overload circuit (OLP) and ensures that all circuits are fully operational when the PVDD and AVDD supply voltages reach 4.5 V and 2.7 V, respectively.
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TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com SERIAL INTERFACE CONTROL AND TIMING I2S Timing I2S timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCLK is low for the left channel and high for the right channel. A bit clock running at 32, 48, or 64 × fS is used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal changes state to the first bit of data on the data lines.
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TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.
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TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com 2-Channel Left-Justified Stereo Input 32 Clks 32 Clks Left Channel Right Channel LRCLK SCLK SCLK MSB 24-Bit Mode 23 22 LSB 9 8 5 4 5 4 1 0 1 0 1 0 MSB LSB 23 22 9 8 5 4 19 18 5 4 1 0 15 14 1 0 1 0 20-Bit Mode 19 18 16-Bit Mode 15 14 T0034-02 NOTE: All data presented in 2s-complement form with MSB first. Figure 29.
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TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com 2-Channel Left-Justified Stereo Input 16 Clks 16 Clks Left Channel Right Channel LRCLK SCLK SCLK MSB 16-Bit Mode 15 14 13 12 LSB 11 10 9 8 5 4 3 2 1 0 MSB 15 14 13 12 LSB 11 10 9 8 5 4 3 2 1 0 T0266-02 NOTE: All data presented in 2s-complement form with MSB first. Figure 31.
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TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com 2-Channel Right-Justified Stereo Input (24-Bit Transfer Word Size) 24 Clks 24 Clks Left Channel Right Channel LRCLK SCLK SCLK MSB 24-Bit Mode 23 22 LSB 19 18 15 14 6 5 2 1 0 19 18 15 14 6 5 2 1 0 15 14 6 5 2 1 0 LSB MSB 23 22 19 18 15 14 6 5 2 1 0 19 18 15 14 6 5 2 1 0 15 14 6 5 2 1 0 20-Bit Mode 16-Bit Mode T0092-03 Figure 33. Right-Justified 48-fS Format Figure 34.
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TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com I2C SERIAL CONTROL INTERFACE The TAS5717/9 DAP has a bidirectional I2C interface that is compatible with the Inter IC (I2C) bus protocol and supports both 100-kHz and 400-kHz data transfer rates for single- and multiple-yte write and read operations. This is a slave-only device that does not support a multimaster bus environment or wait-state insertion.
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TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com Supplying a subaddress for each subaddress transaction is referred to as random I2C addressing. The TAS5717/9 also supports sequential I2C addressing. For write transactions, if a subaddress is issued followed by data for that subaddress and the 15 subaddresses that follow, a sequential I2C write transaction has taken place, and the data for all 16 subaddresses is successfully received by the TAS5717/9.
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TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com Single-Byte Read As shown in Figure 38, a single-byte data-read transfer begins with the master device transmitting a start condition followed by the I2C device address and the read/write bit. For the data-read transfer, both a write followed by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal memory address to be read. As a result, the read/write bit becomes a 0.
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TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com Dynamic Range Control (DRC) The DRC scheme has a single threshold, offset, and slope (all programmable). There is one ganged DRC for the high-band left/right channels and one DRC for the low-band left/right channels. The DRC input/output diagram is shown in Figure 40. See the GDE software tool for more description on the T, K, and O parameters.
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TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com PWM LEVEL METER The structure in Figure 42 shows the PWM level meter that can be used to study the power profile. Post-DAP Processing 1–a –1 Z Ch1 a ABS 32-Bit Level rms ADDR = 0x6B 2 I C Registers (PWM Level Meter) 1–a –1 Z Ch2 a ABS 32-Bit Level rms ADDR = 0x6C B0396-01 Figure 42. PWM Level Meter Structure 26-Bit 3.23 Number Format All mixer gain coefficients are 26-bit coefficients using a 3.23 number format.
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TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com Gain coefficients, entered via the I2C bus, must be entered as 32-bit binary numbers. The format of the 32-bit number (4-byte or 8-digit hexadecimal number) is shown in Figure 45 Fraction Digit 6 Sign Bit Fraction Digit 1 Integer Digit 1 Fraction Digit 2 Fraction Digit 3 Fraction Digit 4 Fraction Digit 5 u u u u u u S x x.
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TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com Table 3. Serial Control Interface Register Summary SUBADDRESS REGISTER NAME NO. OF BYTES INITIALIZATION VALUE CONTENTS A u indicates unused bits.
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TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com Table 3. Serial Control Interface Register Summary (continued) SUBADDRESS 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 34 REGISTER NAME ch1_bq[3] ch1_bq[4] ch1_bq[5] ch1_bq[6] ch1_bq[7] ch1_bq[8] ch1_bq[9] ch2_bq[0] ch2_bq[1] NO.
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TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com Table 3. Serial Control Interface Register Summary (continued) SUBADDRESS 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 REGISTER NAME ch2_bq[2] ch2_bq[3] ch2_bq[4] ch2_bq[5] ch2_bq[6] ch2_bq[7] ch2_bq[8] ch2_bq[9] 0x3A 0x3B DRC1 softening filter alpha NO.
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TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com Table 3. Serial Control Interface Register Summary (continued) SUBADDRESS REGISTER NAME 0x3D 0x3E DRC2 softening filter alpha NO. OF BYTES 8 Reserved (3) 8 u[31:26], ae[25:0] 0x0008 0000 u[31:26], oe[25:0] 0xFFF8 0000 DRC2 softening filter omega 0x3F DRC2 attack rate 8 u[31:26], at[25:0] 0x0008 0000 u[31:26], rt[25:0] 0xFFF8 0000 4 T1[31:0] (9.23 format) 0x0800 0000 4 Reserved (3) 4 T2[31:0] (9.
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TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com Table 3. Serial Control Interface Register Summary (continued) SUBADDRESS 0x5C 0x5D 0x5E 0x5F NO.
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TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com CLOCK CONTROL REGISTER (0x00) The clocks and data rates are automatically determined by the TAS5717/9. The clock control register contains the autodetected clock status. Bits D7–D5 reflect the sample rate. Bits D4–D2 reflect the MCLK frequency. Table 4.
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TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com ERROR STATUS REGISTER (0x02) The error bits are sticky and are not cleared by the hardware. This means that the software must clear the register (write zeroes) and then read them to determine if they are persistent errors. Error definitions: • MCLK error: MCLK frequency is changing. The number of MCLKs per LRCLK is changing. • SCLK error: The number of SCLKs per LRCLK is changing. • LRCLK error: LRCLK frequency is changing.
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TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com SERIAL DATA INTERFACE REGISTER (0x04) As shown in Table 8, the TAS5717/9 supports nine serial data modes. The default is 24-bit, I2S mode. Table 8.
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TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com SYSTEM CONTROL REGISTER 2 (0x05) When bit D6 is set low, the system exits all-channel shutdown and starts playing audio; otherwise, the outputs are shut down (hard mute). Table 9.
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TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com VOLUME REGISTERS (0x07, 0x08, 0x09) Step size is 0.125 dB and volume registers are 2 bytes. Master volume – 0x07 (default is mute) Channel-1 volume – 0x08 (default is 0 dB) Channel-2 volume – 0x09 (default is 0 dB) Headphone volume – 0x0B (default is 0 dB) Table 11. Master Volume Table Value Level Value Level Value Level Value Level Value Level Value Level 0x0000 24.000 0x0027 19.250 0x004E 14.
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TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com Table 11. Master Volume Table (continued) Value Level Value Level Value Level Value Level Value Level Value Level 0x0026 19.125 0x004D 14.375 0x0074 9.500 0x009B 4.625 0x00C2 –0.250 0x00E9 –5.125 0x00EA –5.250 0x0119 –11.125 0x0148 –17.000 0x0177 –22.875 0x01A6 –28.750 0x01D5 –34.625 0x00EB –5.375 0x011A –11.250 0x0149 –17.125 0x0178 –23.000 0x01A7 –28.875 0x01D6 –34.750 0x00EC –5.
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TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com Table 11. Master Volume Table (continued) Value Level Value Level Value Level Value Level Value Level Value Level 0x0118 –11.000 0x0147 –16.875 0x0176 –22.750 0x01A5 –28.625 0x01D4 –34.500 0x0203 –40.375 0x0204 –40.500 0x0233 –46.375 0x0262 –52.250 0x0291 –58.250 0x02C0 –64.000 0x02EF –69.875 0x0205 –40.625 0x0234 –46.500 0x0263 –52.375 0x0292 –58.125 0x02C1 –64.125 0x02F0 –70.
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TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com Table 11. Master Volume Table (continued) Value Level Value Level Value Level Value Level Value Level Value Level 0x0232 –46.250 0x0261 –52.125 0x0290 –58.000 0x02BF –63.875 0x02EE –69.750 0x031D –75.625 0x031E –75.750 0x0344 –80.500 0x036A –85.250 0x0390 –90.000 0x03B6 –94.750 0x03DC –99.500 0x031F –75.875 0x0345 –80.625 0x036B –85.375 0x0391 –90.125 0x03B7 –94.875 0x03DD –99.
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TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com VOLUME CONFIGURATION REGISTER (0x0E) Bits D2–D0: Volume slew rate (used to control volume change and MUTE ramp rates). These bits control the number of steps in a volume ramp. Volume steps occur at a rate that depends on the sample rate of the I2S data as follows: Sample rate (kHz) Approximate ramp rate 8/16/32 125 μs/step 11.025/22.05/44.1 90.7 μs/step 12/24/48 83.3 μs/step Table 12.
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TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com INTERCHANNEL DELAY REGISTERS (0x11, 0x12, 0x13, and 0x14) Internal PWM channels 1, 2, 1, and 2 are mapped into registers 0x11, 0x12, 0x13, and 0x14. Table 14.
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TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com PWM SHUTDOWN GROUP REGISTER (0x19) Settings of this register determine which PWM channels are active. The value should be 0x30 for BTL mode and 0x3A for PBTL mode. The default value of this register is 0x30. The functionality of this register is tied to the state of bit D5 in the system control register. This register defines which channels belong to the shutdown group (SDG).
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TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com START/STOP PERIOD REGISTER (0x1A) This register is used to control the soft-start and soft-stop period following an enter/exit all-channel shutdown command or change in the PDN state. This helps reduce pops and clicks at start-up and shutdown. The times are only approximate and vary depending on device activity level and I2S clock stability. Table 16.
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TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com OSCILLATOR TRIM REGISTER (0x1B) The TAS5717/9 PWM processor contains an internal oscillator to support autodetect of I2S clock rates. This reduces system cost because an external reference is not required. Currently, TI recommends a reference resistor value of 18.2 kΩ (1%). This should be connected between OSC_RES and DVSSO. Writing 0x00 to register 0x1B enables the trim that was programmed at the factory.
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TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com Table 18.
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TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com INPUT MULTIPLEXER REGISTER (0x20) This register controls the modulation scheme (AD or BD mode) as well as the routing of I2S audio to the internal channels. Table 19.
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TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com CHANNEL 4 SOURCE SELECT REGISTER (0x21) This register selects the channel 4 source. Table 20.
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TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com Table 21.
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TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com PWM SWITCHING RATE CONTROL REGISTER (0x4F) PWM switching rate should be selected through the register 0x4F before coming out of all-channnel shutdown. Table 23.
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TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com USING HEADPHONE AMPLIFIER IN TAS5717 This device has a stereo output which can be used as a line driver or a headphone driver that can output 2-Vrms stereo. An audio system can be set up for different applications using this device.
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TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com APPLICATION INFORMATION LINE DRIVER AMPLIFIERS Single-supply headphone and line driver amplifiers typically require dc-blocking capacitors. The top drawing in Figure 47 illustrates the conventional line driver amplifier connection to the load and output signal.
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TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com Decoupling Capacitors The TAS5717/9 is a DirectPath™ amplifier that requires adequate power supply decoupling to ensure that the noise and total harmonic distortion (THD) are low. A good low equivalent-series-resistance (ESR) ceramic capacitor, typically 1µF, placed as close as possible to the device PVDD leads works best. Placing this decoupling capacitor close to the TAS5717/9 is important for the performance of the amplifier.
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TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com The component values can be calculated with the help of the TI FilterPro™ program available on the TI website at: http://focus.ti.com/docs/toolsw/folders/print/filterpro.html Inverting Input R2 C3 R1 C1 R3 –In – C2 TAS5717 + S0447-01 Figure 49.
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TAS5717 TAS5719 SLOS655A – NOVEMBER 2010 – REVISED FEBRUARY 2011 www.ti.com REVISION HISTORY Changes from Original (November 2010) to Revision A Page • Changed the SNR typ value from 70°C to 105°C ............................................................................................................... 10 • Deleted sub section titled 11.12 BANK SWITCHING .........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 30-Jun-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.com 20-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TAS5717PHPR HTQFP PHP 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2 TAS5719PHPR HTQFP PHP 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 20-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TAS5717PHPR HTQFP PHP 48 1000 367.0 367.0 38.0 TAS5719PHPR HTQFP PHP 48 1000 367.0 367.0 38.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.