Datasheet

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TAS5727

www.ti.com

SLOS670 –NOVEMBER 2010

25-W DIGITAL AUDIO POWER AMPLIFIER WITH EQ AND DRC

Check for Samples: TAS5727

FEATURES

• Audio Input/Output – Up to 90% Efficient

– 25 W Into an 8-Ω Load From a 20-V Supply – PWM Level Meter to Measure the Digital

Power Profile

– Wide PVDD Range, From 8 V to 26 V

– Supports BTL Configuration With 4-Ω Load

• Benefits

– Efficient Class-D Operation Eliminates

– EQ: Speaker Equalization Improves Audio

Need for Heatsinks

Performance

– One Serial Audio Input (Two Audio

– Two-Band DRC: Dynamic Range

Channels)

Compression. Can Be Used As Power

– I

C Address Selection Pin (Chip Select)

Limiter. Enables Speaker Protection, Easy

– Single Output Filter PBTL Support

Listening, Night-Mode Listening

– Supports 44.1-kHz to 48-kHz Sample Rate

– Autodetect: Automatically Detects

(LJ/RJ/I

Sample-Rate Changes. No Need for

• Audio/PWM Processing

External Microprocessor Intervention

– Independent Channel Volume Controls With

Gain of 24 dB to Mute With 0.125-dB APPLICATIONS

Resolution Steps

• LCD TV, LED TV, Soundbar

– Programmable Two-Band Dynamic-Range

DESCRIPTION

Control

– 18 Programmable Biquads for Speaker EQ

The TAS5727 is a 25-W, efficient, digital-audio power

and Other Audio-Processing Features

amplifier for driving stereo bridge-tied speakers. One

serial data input allows processing of up to two

– Programmable Coefficients for DRC Filters

discrete audio channels and seamless integration to

– DC Blocking Filters

most digital audio processors and MPEG decoders.

• General Features

The device accepts a wide range of input data and

data rates. A fully programmable data path routes

– I

C Serial Control Interface Operational

these channels to the internal speaker drivers.

Without MCLK

The TAS5727 is a slave-only device receiving all

– Requires Only 3.3 V and PVDD

clocks from external sources. The TAS5727 operates

– No External Oscillator: Internal Oscillator

with a PWM carrier between a 384-kHz switching rate

for Automatic Rate Detection

and a 288-KHz switching rate, depending on the input

– Surface-Mount, 48-Pin HTQFP Package

sample rate. Oversampling combined with a

fourth-order noise shaper provides a flat noise floor

– Thermal and Short-Circuit Protection

and excellent dynamic range from 20 Hz to 20 kHz.

– 106-dB SNR, A-Weighted

– AD, BD, and Ternary Modulation

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (61 pages)

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TAS5727 www.ti.com SLOS670 – NOVEMBER 2010 25-W DIGITAL AUDIO POWER AMPLIFIER WITH EQ AND DRC Check for Samples: TAS5727 FEATURES 1 • • • Audio Input/Output – 25 W Into an 8-Ω Load From a 20-V Supply – Wide PVDD Range, From 8 V to 26 V – Supports BTL Configuration With 4-Ω Load – Efficient Class-D Operation Eliminates Need for Heatsinks – One Serial Audio Input (Two Audio Channels) – I2C Address Selection Pin (Chip Select) – Single Output Filter PBTL Support – Supports 44.
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TAS5727 SLOS670 – NOVEMBER 2010 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. SIMPLIFIED APPLICATION DIAGRAM 3.
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TAS5727 www.ti.
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TAS5727 SLOS670 – NOVEMBER 2010 www.ti.com FAULT Undervoltage Protection FAULT 4 4 Power On Reset Protection and I/O Logic AGND Temp.
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R L 1BQ 30 1BQ 26 0x77 0x76 0x73 0x72 9BQ 31–39 9BQ 27–2F Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): TAS5727 2BQ 5A, 5B 2BQ 5E, 5F 2BQ 5C, 5D 2BQ 58, 59 0x75 0x74 v2im1 0x71 0x70 2 Vol Vol Vol2 Vol1 0x46[1] 0x46[0] Vol Config Reg 0x0E AGL AGL I C Subaddress in Red 0x52[0] 0x52[1] 0x51[0] 0x51[1] 2 2 32 Level Meter clip24 clip24 2 I C:0x6B (32Bit-Left Level) 32 32 32 I C:0x6C (32 Bit-Right Level) I C:57 VDISTB 2 I C:56 VDIS
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TAS5727 SLOS670 – NOVEMBER 2010 www.ti.
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TAS5727 www.ti.com SLOS670 – NOVEMBER 2010 PIN FUNCTIONS (continued) PIN NAME NO.
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TAS5727 SLOS670 – NOVEMBER 2010 www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) DVDD, AVDD Supply voltage PVDD_x 3.3-V digital input Input voltage VALUE UNIT –0.3 to 3.6 V –0.3 to 30 V –0.5 to DVDD + 0.5 5-V tolerant (2) digital input (except MCLK) –0.5 to DVDD + 2.5 (3) 5-V tolerant MCLK input –0.5 to AVDD + 2.
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TAS5727 www.ti.com SLOS670 – NOVEMBER 2010 PLL INPUT PARAMETERS AND EXTERNAL FILTER COMPONENTS PARAMETER fMCLKI tr / tf(MCLK) TEST CONDITIONS MIN MCLK frequency 2.8224 MCLK duty cycle 40% TYP 50% Rise/fall time for MCLK LRCLK allowable drift before LRCLK reset External PLL filter capacitor C1 SMD 0603 X7R External PLL filter capacitor C2 External PLL filter resistor R MAX UNIT 24.576 MHz 60% 5 ns 4 MCLKs 47 nF SMD 0603 X7R 4.
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TAS5727 SLOS670 – NOVEMBER 2010 www.ti.com AC Characteristics (BTL, PBTL) PVDD_x = 18 V, BTL AD mode, fS = 48 KHz, RL = 8 Ω, ROCP = 22 kΩ, CBST = 33 nF, audio frequency = 1 kHz, AES17 filter, fPWM = 384 kHz, TA = 25°C (unless otherwise specified). All performance is in accordance with recommended operating conditions (unless otherwise specified). PARAMETER TEST CONDITIONS MIN PVDD = 18 V,10% THD, 1-kHz input signal 21.5 PVDD = 18 V, 7% THD, 1-kHz input signal 20.
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TAS5727 www.ti.com SLOS670 – NOVEMBER 2010 SERIAL AUDIO PORTS SLAVE MODE over recommended operating conditions (unless otherwise noted) TEST CONDITIONS PARAMETER MIN CL = 30 pF TYP 1.024 MAX UNIT 12.
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TAS5727 SLOS670 – NOVEMBER 2010 www.ti.com I2C SERIAL CONTROL PORT OPERATION Timing characteristics for I2C Interface signals over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN No wait states MAX UNIT 400 kHz fSCL Frequency, SCL tw(H) Pulse duration, SCL high 0.6 tw(L) Pulse duration, SCL low 1.
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TAS5727 www.ti.com SLOS670 – NOVEMBER 2010 RESET TIMING (RESET) Control signal parameters over recommended operating conditions (unless otherwise noted). Please refer to Recommended Use Model section on usage of all terminals. PARAMETER tw(RESET) Pulse duration, RESET active td(I2C_ready) Time to enable I2C MIN TYP MAX UNIT 100 ms 12 ms RESET tw(RESET) 2 2 I C Active I C Active td(I2C_ready) System Initialization. 2 Enable via I C.
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TAS5727 SLOS670 – NOVEMBER 2010 www.ti.com TYPICAL CHARACTERISTICS, BTL CONFIGURATION, 8 Ω TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY TOTAL HARMONIC DISTORTION + NOISE vs FREQUENCY 10 10 PVDD = 12V RL = 8Ω TA = 25°C PVDD = 18V RL = 8Ω TA = 25°C 1 THD+N (%) THD+N (%) 1 0.1 0.01 0.1 0.01 PO = 1W PO = 2.5W PO = 5W 0.001 20 100 PO = 1W PO = 5W PO = 10W 1k Frequency (Hz) 10k 0.001 20k 100 1k Frequency (Hz) Figure 7.
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TAS5727 www.ti.com SLOS670 – NOVEMBER 2010 TYPICAL CHARACTERISTICS, BTL CONFIGURATION, 8 Ω (continued) TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER TOTAL HARMONIC DISTORTION + NOISE vs OUTPUT POWER 10 10 PVDD = 18V RL = 8Ω TA = 25°C PVDD = 24V RL = 8Ω TA = 25°C 1 THD+N (%) THD+N (%) 1 0.1 0.1 0.01 0.01 f = 20Hz f = 1kHz f = 10kHz 0.001 0.01 0.1 1 Output Power (W) 10 40 f = 20Hz f = 1kHz f = 10kHz 0.001 0.01 Figure 11.
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TAS5727 SLOS670 – NOVEMBER 2010 www.ti.com TYPICAL CHARACTERISTICS, BTL CONFIGURATION, 8 Ω (continued) CROSSTALK vs FREQUENCY EFFICIENCY vs TOTAL OUTPUT POWER 0 100 VO = 1W PVDD = 24V RL = 8Ω TA = 25°C −10 90 80 −30 70 −40 60 Efficiency (%) Crosstalk (dB) −20 Right to Left Left to Right −50 −60 50 40 −70 30 −80 20 −90 10 −100 20 100 1k Frequency (Hz) Figure 14.
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TAS5727 www.ti.com SLOS670 – NOVEMBER 2010 I2C CHIP SELECT A_SEL_FAULT is an input pin during power up. It can be pulled high (15-kΩ pullup) or low (15-kΩ pulldown). High indicates an I2C subaddress of 0x56, and low a subaddress of 0x54. I2C Device Address Change Procedure • Write to device address change enable register, 0xF8 with a value of 0xF9A5 A5A5. • Write to device register 0xF9 with a value of 0x0000 00XX, where XX is the new address.
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TAS5727 SLOS670 – NOVEMBER 2010 www.ti.com Table 1. A_SEL_FAULT Output States A_SEL_FAULT DESCRIPTION 0 Overcurrent (OC) or undervoltage (UVP) error or overtemperature error (OTE) or overvoltage error 1 No faults (normal operation) SSTIMER FUNCTIONALITY The SSTIMER pin uses a capacitor connected between this pin and ground to control the output duty cycle when exiting all-channel shutdown.
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TAS5727 www.ti.com SLOS670 – NOVEMBER 2010 SERIAL INTERFACE CONTROL AND TIMING I2S Timing I2S timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCLK is low for the left channel and high for the right channel. A bit clock running at 32, 48, or 64 × fS is used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal changes state to the first bit of data on the data lines.
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TAS5727 SLOS670 – NOVEMBER 2010 www.ti.com 2 2-Channel I S (Philips Format) Stereo Input/Output (24-Bit Transfer Word Size) LRCLK 24 Clks 24 Clks Left Channel Right Channel SCLK SCLK MSB 24-Bit Mode 23 22 MSB LSB 17 16 9 8 5 4 13 12 5 4 1 0 9 1 0 3 2 1 0 LSB 23 22 17 16 9 8 5 4 19 18 13 12 5 4 1 0 15 14 9 1 0 3 2 1 20-Bit Mode 19 18 16-Bit Mode 15 14 8 8 T0092-01 NOTE: All data presented in 2s-complement form with MSB first. Figure 17.
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TAS5727 www.ti.com SLOS670 – NOVEMBER 2010 2-Channel Left-Justified Stereo Input 32 Clks 32 Clks Left Channel Right Channel LRCLK SCLK SCLK MSB 24-Bit Mode 23 22 LSB 9 8 5 4 5 4 1 0 1 0 1 0 MSB LSB 23 22 9 8 5 4 19 18 5 4 1 0 15 14 1 0 1 0 20-Bit Mode 19 18 16-Bit Mode 15 14 T0034-02 NOTE: All data presented in 2s-complement form with MSB first. Figure 19.
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TAS5727 SLOS670 – NOVEMBER 2010 www.ti.com 2-Channel Left-Justified Stereo Input 16 Clks 16 Clks Left Channel Right Channel LRCLK SCLK SCLK MSB 16-Bit Mode 15 14 13 12 LSB 11 10 9 8 5 4 3 2 1 0 MSB 15 14 13 12 LSB 11 10 9 8 5 4 3 2 1 0 T0266-02 NOTE: All data presented in 2s-complement form with MSB first. Figure 21.
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TAS5727 www.ti.com SLOS670 – NOVEMBER 2010 2-Channel Right-Justified Stereo Input (24-Bit Transfer Word Size) 24 Clks 24 Clks Left Channel Right Channel LRCLK SCLK SCLK MSB 24-Bit Mode 23 22 LSB 19 18 15 14 6 5 2 1 0 19 18 15 14 6 5 2 1 0 15 14 6 5 2 1 0 LSB MSB 23 22 19 18 15 14 6 5 2 1 0 19 18 15 14 6 5 2 1 0 15 14 6 5 2 1 0 20-Bit Mode 16-Bit Mode T0092-03 Figure 23. Right-Justified 48-fS Format Figure 24.
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TAS5727 SLOS670 – NOVEMBER 2010 www.ti.com I2C SERIAL CONTROL INTERFACE The TAS5727 DAP has a bidirectional I2C interface that is compatible with the Inter IC (I2C) bus protocol and supports both 100-kHz and 400-kHz data transfer rates for single- and multiple-byte write and read operations. This is a slave-only device that does not support a multimaster bus environment or wait-state insertion. The control interface is used to program the registers of the device and to read device status.
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TAS5727 www.ti.com SLOS670 – NOVEMBER 2010 Supplying a subaddress for each subaddress transaction is referred to as random I2C addressing. The TAS5727 also supports sequential I2C addressing. For write transactions, if a subaddress is issued followed by data for that subaddress and the 15 subaddresses that follow, a sequential I2C write transaction has taken place, and the data for all 16 subaddresses is successfully received by the TAS5727.
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TAS5727 SLOS670 – NOVEMBER 2010 www.ti.com Single-Byte Read As shown in Figure 28, a single-byte data-read transfer begins with the master device transmitting a start condition, followed by the I2C device address and the read/write bit. For the data read transfer, both a write followed by a read are actually done. Initially, a write is done to transfer the address byte or bytes of the internal memory address to be read. As a result, the read/write bit becomes a 0.
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TAS5727 www.ti.com SLOS670 – NOVEMBER 2010 Dynamic Range Control (DRC) The DRC scheme has two DRC blocks. There is one ganged DRC for the high-band left/right channels and one DRC for the low-band left/right channels. Output Level (dB) The DRC input/output diagram is shown in Figure 30. 1:1 Transfer Function Implemented Transfer Function T Input Level (dB) M0091-04 Professional-quality dynamic range compression automatically adjusts volume to flatten volume level.
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TAS5727 SLOS670 – NOVEMBER 2010 www.ti.com PWM LEVEL METER The structure in Figure 32 shows the PWM level meter that can be used to study the power profile. Post-DAP Processing 1–a –1 Z Ch1 a ABS 32-Bit Level rms ADDR = 0x6B 2 I C Registers (PWM Level Meter) 1–a –1 Z Ch2 a ABS 32-Bit Level rms ADDR = 0x6C B0396-01 Figure 32. PWM Level Meter Structure 26-Bit 3.23 Number Format All mixer gain coefficients are 26-bit coefficients using a 3.23 number format. Numbers formatted as 3.
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TAS5727 www.ti.com SLOS670 – NOVEMBER 2010 Gain coefficients, entered via the I2C bus, must be entered as 32-bit binary numbers. The format of the 32-bit number (4-byte or 8-digit hexadecimal number) is shown in Figure 35. Fraction Digit 6 Sign Bit Fraction Digit 1 Integer Digit 1 Fraction Digit 2 Fraction Digit 3 Fraction Digit 4 Fraction Digit 5 u u u u u u S x x.
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2 Submit Documentation Feedback Product Folder Link(s): TAS5727 PVDD RESET SCL SDA 0 ns 0 ns 100 ms 100 μs 3V 10 ms 8V 6V 13.5 ms Trim 50 ms DAP Config Other Config (1) tPLL has to be greater than 240 ms + 1.3 tstart. This constraint only applies to the first trim command following AVDD/DVDD power-up. It does not apply to trim commands following subsequent resets.
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TAS5727 www.ti.com SLOS670 – NOVEMBER 2010 3V AVDD/DVDD 0 ns 2 ms PDN 0 ns 2 I C 2 ms RESET 2 ms 0 ns 8V PVDD 6V T0420-05 Figure 37. Power-Loss Sequence Initialization Sequence Use the following sequence to power up and initialize the device: 1. Hold all digital inputs low and ramp up AVDD/DVDD to at least 3 V. 2. Initialize digital inputs and PVDD supply as follows: • Drive RESET = 0, PDN = 1, and other digital inputs to their desired state while ensuring that all are never more than 2.
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TAS5727 SLOS670 – NOVEMBER 2010 www.ti.com Shutdown Sequence Enter: 1. Write 0x40 to register 0x05. 2. Wait at least 1 ms + 1.3 × tstop (where tstop is specified by register 0x1A). 3. If desired, reconfigure by returning to step 4 of initialization sequence. 1. Write 0x00 to register 0x05 (exit shutdown command may not be serviced for as much as 240 ms after trim following AVDD/DVDD power-up ramp). 2. Wait at least 1 ms + 1.3 × tstart (where tstart is specified by register 0x1A). 3.
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TAS5727 www.ti.com SLOS670 – NOVEMBER 2010 Table 4. Serial Control Interface Register Summary SUBADDRESS REGISTER NAME NO. OF BYTES INITIALIZATION VALUE CONTENTS A u indicates unused bits.
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TAS5727 SLOS670 – NOVEMBER 2010 www.ti.com Table 4. Serial Control Interface Register Summary (continued) SUBADDRESS 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 34 REGISTER NAME ch1_bq[3] ch1_bq[4] ch1_bq[5] ch1_bq[6] ch1_bq[7] ch1_bq[8] ch1_bq[9] ch2_bq[0] ch2_bq[1] NO.
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TAS5727 www.ti.com SLOS670 – NOVEMBER 2010 Table 4. Serial Control Interface Register Summary (continued) SUBADDRESS 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 REGISTER NAME ch2_bq[2] ch2_bq[3] ch2_bq[4] ch2_bq[5] ch2_bq[6] ch2_bq[7] ch2_bq[8] ch2_bq[9] 0x3A 0x3B DRC1 softening filter alpha NO.
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TAS5727 SLOS670 – NOVEMBER 2010 www.ti.com Table 4. Serial Control Interface Register Summary (continued) SUBADDRESS REGISTER NAME 0x3D 0x3E DRC2 softening filter alpha NO. OF BYTES DRC2 attack rate Reserved (3) 8 u[31:26], ae[25:0] 0x0008 0000 u[31:26], oe[25:0] 0xFFF8 0000 8 u[31:26], at[25:0] 0x0008 0000 u[31:26], rt[25:0] 0xFFF8 0000 4 T1[31:0] (9.23 format) 0x0800 0000 4 Reserved (3) 4 T2[31:0] (9.
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TAS5727 www.ti.com SLOS670 – NOVEMBER 2010 Table 4. Serial Control Interface Register Summary (continued) SUBADDRESS 0x5C 0x5D 0x5E 0x5F REGISTER NAME ch2_bq[10] ch2_bq[11] ch3_bq[0] ch3_bq[1] 0x60–0x61 0x62 NO.
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TAS5727 SLOS670 – NOVEMBER 2010 www.ti.com CLOCK CONTROL REGISTER (0x00) The clocks and data rates are automatically determined by the TAS5727. The clock control register contains the autodetected clock status. Bits D7–D5 reflect the sample rate. Bits D4–D2 reflect the MCLK frequency. Table 5. Clock Control Register (0x00) D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 – – – – – fS = 32-kHz sample rate 0 0 1 – – – – – Reserved 0 1 0 – – – – – Reserved 0 1 1 – – – – – fS = 44.
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TAS5727 www.ti.com SLOS670 – NOVEMBER 2010 ERROR STATUS REGISTER (0x02) The error bits are sticky and are not cleared by the hardware. This means that the software must clear the register (write zeroes) and then read them to determine if they are persistent errors. Error definitions: • MCLK error: MCLK frequency is changing. The number of MCLKs per LRCLK is changing. • SCLK error: The number of SCLKs per LRCLK is changing. • LRCLK error: LRCLK frequency is changing.
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TAS5727 SLOS670 – NOVEMBER 2010 www.ti.com SERIAL DATA INTERFACE REGISTER (0x04) As shown in Table 9, the TAS5727 supports nine serial data modes. The default is 24-bit, I2S mode. Table 9.
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TAS5727 www.ti.com SLOS670 – NOVEMBER 2010 SYSTEM CONTROL REGISTER 2 (0x05) When bit D6 is set low, the system exits all-channel shutdown and starts playing audio; otherwise, the outputs are shut down (hard mute). Table 10.
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TAS5727 SLOS670 – NOVEMBER 2010 www.ti.com VOLUME REGISTERS (0x07, 0x08, 0x09) Step size is 0.125 dB and volume registers are 2 bytes. Master volume – 0x07 (default is mute) Channel-1 volume – 0x08 (default is 0 dB) Channel-2 volume – 0x09 (default is 0 dB) Table 12. Master Volume Table Value Level Value Level Value Level Value Level Value Level Value Level 0x0000 24.000 0x0027 19.250 0x004E 14.250 0x0075 9.375 0x009C 4.500 0x00C3 –0.375 0x0001 23.875 0x0028 19.
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TAS5727 www.ti.com SLOS670 – NOVEMBER 2010 Table 12. Master Volume Table (continued) Value Level Value Level Value Level Value Level Value Level Value Level 0x00EA –5.250 0x0119 –11.125 0x0148 –17.000 0x0177 –22.875 0x01A6 –28.750 0x01D5 –34.625 0x00EB –5.375 0x011A –11.250 0x0149 –17.125 0x0178 –23.000 0x01A7 –28.875 0x01D6 –34.750 0x00EC –5.500 0x011B –11.375 0x014A –17.250 0x0179 –23.125 0x01A8 –29.000 0x01D7 –34.875 0x00ED –5.625 0x011C –11.
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TAS5727 SLOS670 – NOVEMBER 2010 www.ti.com Table 12. Master Volume Table (continued) Value Level Value Level Value Level Value Level Value Level Value Level 0x0204 –40.500 0x0233 –46.375 0x0262 –52.250 0x0291 –58.250 0x02C0 –64.000 0x02EF –69.875 0x0205 –40.625 0x0234 –46.500 0x0263 –52.375 0x0292 –58.125 0x02C1 –64.125 0x02F0 –70.000 0x0206 –40.750 0x0235 –46.625 0x0264 –52.500 0x0293 –58.375 0x02C2 –64.250 0x02F1 –70.125 0x0207 –40.875 0x0236 –46.
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TAS5727 www.ti.com SLOS670 – NOVEMBER 2010 Table 12. Master Volume Table (continued) Value Level Value Level Value Level Value Level Value Level Value Level 0x031E –75.750 0x0344 –80.500 0x036A –85.250 0x0390 –90.000 0x03B6 –94.750 0x03DC –99.500 0x031F –75.875 0x0345 –80.625 0x036B –85.375 0x0391 –90.125 0x03B7 –94.875 0x03DD –99.625 0x0320 –76.000 0x0346 –80.750 0x036C –85.500 0x0392 –90.250 0x03B8 –95.000 0x03DE –99.750 0x0321 –76.125 0x0347 –80.
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TAS5727 SLOS670 – NOVEMBER 2010 www.ti.com VOLUME CONFIGURATION REGISTER (0x0E) Bits D2–D0: Volume slew rate (used to control volume change and MUTE ramp rates). These bits control the number of steps in a volume ramp. Volume steps occur at a rate that depends on the sample rate of the I2S data as follows: Sample rate (kHz) Approximate ramp rate 8/16/32 125 ms/step 11.025/22.05/44.1 90.7 ms/step 12/24/48 83.
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TAS5727 www.ti.com SLOS670 – NOVEMBER 2010 INTERCHANNEL DELAY REGISTERS (0x11, 0x12, 0x13, and 0x14) Internal PWM channels 1, 2, 1, and 2 are mapped into registers 0x11, 0x12, 0x13, and 0x14. Table 15.
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TAS5727 SLOS670 – NOVEMBER 2010 www.ti.com PWM SHUTDOWN GROUP REGISTER (0x19) Settings of this register determine which PWM channels are active. The value should be 0x30 for BTL mode and 0x3A for PBTL mode. The default value of this register is 0x30. The functionality of this register is tied to the state of bit D5 in the system control register. This register defines which channels belong to the shutdown group (SDG).
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TAS5727 www.ti.com SLOS670 – NOVEMBER 2010 START/STOP PERIOD REGISTER (0x1A) This register is used to control the soft-start and soft-stop period following an enter/exit all-channel shutdown command or change in the PDN state. This helps reduce pops and clicks at start-up and shutdown. The times are only approximate and vary depending on device activity level and I2S clock stability. Table 17.
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TAS5727 SLOS670 – NOVEMBER 2010 www.ti.com OSCILLATOR TRIM REGISTER (0x1B) The TAS5727 PWM processor contains an internal oscillator to support autodetect of I2S clock rates. This reduces system cost because an external reference is not required. Currently, TI recommends a reference resistor value of 18.2 kΩ (1%). This should be connected between OSC_RES and DVSSO. Writing 0x00 to register 0x1B enables the trim that was programmed at the factory.
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TAS5727 www.ti.com SLOS670 – NOVEMBER 2010 INPUT MULTIPLEXER REGISTER (0x20) This register controls the modulation scheme (AD or BD mode) as well as the routing of I2S audio to the internal channels. Table 20.
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TAS5727 SLOS670 – NOVEMBER 2010 www.ti.com CHANNEL 4 SOURCE SELECT REGISTER (0x21) This register selects the channel 4 source. Table 21.
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TAS5727 www.ti.com SLOS670 – NOVEMBER 2010 Table 22.
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TAS5727 SLOS670 – NOVEMBER 2010 www.ti.com PWM SWITCHING RATE CONTROL REGISTER (0x4F) PWM switching rate should be selected through the register 0x4F before coming out of all-channnel shutdown. Table 24.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 19-Jun-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device TAS5727PHPR Package Package Pins Type Drawing HTQFP PHP 48 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 16.4 Pack Materials-Page 1 9.6 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 9.6 1.5 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 19-Jun-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TAS5727PHPR HTQFP PHP 48 1000 367.0 367.0 38.
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