Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsInterface ICsInterface IC - I/O extensions POR I²C, SMBus 400 kHz UQFN 32 Exposed Pad

ADDR

P20

P21

P22

P23

P24

P25

P26

P27

RESET

P00

P01

P02

P03

P04

P05

P06

P07

CCI

GND

INT

CCP

SDA

P17

P16

P15

P14

P13

P10

P11

P12

SCL

Exposed

Center Pad

TCA6424A

www.ti.com

SCPS193B –JULY 2010–REVISED SEPTEMBER 2010

LOW-VOLTAGE 24-BIT I

C AND SMBus I/O EXPANDER

WITH INTERRUPT OUTPUT, RESET, AND CONFIGURATION REGISTERS

Check for Samples: TCA6424A

FEATURES

• Operating Power-Supply Voltage Range of • Polarity Inversion Register

1.65 V to 5.5 V

• Internal Power-On Reset

• Allows Bidirectional Voltage-Level Translation

• Power Up With All Channels Configured as

and GPIO Expansion Between:

Inputs

– 1.8-V SCL/SDA and

• No Glitch On Power Up

1.8-V, 2.5-V, 3.3-V, or 5-V P Port

• Noise Filter on SCL/SDA Inputs

– 2.5-V SCL/SDA and

• Latched Outputs With High-Current Drive

1.8-V, 2.5-V, 3.3-V, or 5-V P Port

Maximum Capability for Directly Driving LEDs

– 3.3-V SCL/SDA and

• Latch-Up Performance Exceeds 100 mA Per

1.8-V, 2.5-V, 3.3-V, or 5-V P Port

JESD 78, Class II

– 5-V SCL/SDA and

• ESD Protection Exceeds JESD 22

1.8-V, 2.5-V, 3.3-V, or 5-V P Port

– 2000-V Human-Body Model (A114-A)

• I

C to Parallel Port Expander

– 200-V Machine Model (A115-A)

• Low Standby Current Consumption of 1 mA

– 1000-V Charged-Device Model (C101)

• Schmitt-Trigger Action Allows Slow Input

Transition and Better Switching Noise

RGJ/RSM PACKAGE

(BOTTOM VIEW)

Immunity at the SCL and SDA Inputs

– V

hys

= 0.18 V Typ at 1.8 V

– V

hys

= 0.25 V Typ at 2.5 V

– V

hys

= 0.33 V Typ at 3.3 V

– V

hys

= 0.5 V Typ at 5 V

• 5-V Tolerant I/O Ports

• Active-Low Reset Input (RESET)

• Open-Drain Active-Low Interrupt Output (INT)

• 400-kHz Fast I

C Bus

• Input/Output Configuration Register

If used, the exposed center pad must be

connected as a secondary ground or left

electrically open.

DESCRIPTION/ORDERING INFORMATION

This 24-bit I/O expander for the two-line bidirectional bus (I

C) is designed to provide general-purpose remote I/O

expansion for most microcontroller families via the I

C interface [serial clock (SCL) and serial data (SDA)].

The major benefit of this device is its wide V

range. It can operate from 1.65 V to 5.5 V on the P-port side and

on the SDA/SCL side. This allows the TCA6424A to interface with next-generation microprocessors and

microcontrollers on the SDA/SCL side, where supply levels are dropping down to conserve power. In contrast to

the dropping power supplies of microprocessors and microcontrollers, some PCB components, such as LEDs,

remain at a 5-V power supply.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (35 pages)

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TCA6424A www.ti.
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TCA6424A SCPS193B – JULY 2010 – REVISED SEPTEMBER 2010 www.ti.com DESCRIPTION/ORDERING INFORMATION (CONTINUED) The bidirectional voltage level translation in the TCA6424A is provided through VCCI. VCCI should be connected to the VCC of the external SCL/SDA lines. This indicates the VCC level of the I2C bus to the TCA6424A. The voltage level on the P-port of the TCA6424A is determined by the VCCP.
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TCA6424A www.ti.com SCPS193B – JULY 2010 – REVISED SEPTEMBER 2010 Table 1. TERMINAL FUNCTIONS TERMINAL DESCRIPTION PIN NO. NAME 1 P00 P-port input/output (push-pull design structure). At power on, P00 is configured as an input. 2 P01 P-port input/output (push-pull design structure). At power on, P01 is configured as an input. 3 P02 P-port input/output (push-pull design structure). At power on, P02 is configured as an input. 4 P03 P-port input/output (push-pull design structure).
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TCA6424A SCPS193B – JULY 2010 – REVISED SEPTEMBER 2010 www.ti.com Table 2. Voltage Translation VCCI (SDA AND SCL OF I2C MASTER) (V) VCCP (P PORT) (V) 1.8 1.8 1.8 2.5 1.8 3.3 1.8 5 2.5 1.8 2.5 2.5 2.5 3.3 2.5 5 3.3 1.8 3.3 2.5 3.3 3.3 3.3 5 5 1.8 5 2.5 5 3.
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TCA6424A www.ti.
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TCA6424A SCPS193B – JULY 2010 – REVISED SEPTEMBER 2010 www.ti.com I/O Port When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a high-impedance input. The input voltage may be raised above VCC to a maximum of 5.5 V. If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the output port register. In this case, there are low-impedance paths between the I/O pin and either VCC or GND.
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TCA6424A www.ti.com SCPS193B – JULY 2010 – REVISED SEPTEMBER 2010 Data Output by Transmitter NACK Data Output by Receiver ACK SCL From Master 1 2 8 9 S Clock Pulse for Acknowledgment Start Condition Figure 3. Acknowledgment on the I2C Bus Table 3.
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TCA6424A SCPS193B – JULY 2010 – REVISED SEPTEMBER 2010 www.ti.com The control register includes an Auto-Increment (AI) bit which is the most significant bit (bit 7) of the command byte. At power-up, the control register defaults to 00 (hex), with the AI bit set to logic 1, and the lowest 7 bits set to logic 0. If AI is 1, the 2 least significant bits are automatically incremented after a read or write. This allows the user to program and/or read the 3 register banks sequentially.
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TCA6424A www.ti.com SCPS193B – JULY 2010 – REVISED SEPTEMBER 2010 Table 5.
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TCA6424A SCPS193B – JULY 2010 – REVISED SEPTEMBER 2010 www.ti.com Register Descriptions The Input Port registers (registers 0, 1 and 2) reflect the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the Configuration register. They act only on read operation. Writes to these registers have no effect. The default value (X) is determined by the externally applied logic level.
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TCA6424A www.ti.com SCPS193B – JULY 2010 – REVISED SEPTEMBER 2010 Power-On Reset When power (from 0 V) is applied to VCCP, an internal power-on reset holds the TCA6424A in a reset condition until VCCP has reached VPOR. At that time, the reset condition is released, and the TCA6424A registers and I2C/SMBus state machine initializes to their default states. After that, VCCP must be lowered to below 0.2 V and back up to the operating voltage for a power-reset cycle.
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TCA6424A SCPS193B – JULY 2010 – REVISED SEPTEMBER 2010 SCL 1 2 3 4 5 6 7 8 9 Command Byte Slave Address SDA 0 S 1 0 0 0 www.ti.com 1 AD DR 0 A 0 0 0 0 0 Data to Port 0 1 0/1 0/1 A 0.7 R/W Acknowledge From Slave Start Condition Data to Port 1 0.0 A 1.7 Data 0 Acknowledge From Slave Data 1 1.0 A P Acknowledge From Slave Write to Port Data Out from Port 0 tpv Data Valid Data Out from Port 1 tpv Figure 6.
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TCA6424A www.ti.com SCPS193B – JULY 2010 – REVISED SEPTEMBER 2010 Slave Address S 0 0 1 0 0 Acknowledge From Slave Acknowledge From Slave 1 AD DR 0 Command Byte A R/W A S Acknowledge From Slave Slave Address 0 1 0 0 0 AD 1 DR 1 Data A MSB LSB A First Byte R/W At this moment, master transmitter becomes master receiver, and slave receiver becomes slave transmitter.
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TCA6424A SCPS193B – JULY 2010 – REVISED SEPTEMBER 2010 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCCI Supply voltage range –0.5 6.5 V VCCP Supply voltage range –0.5 6.5 V VI Input voltage range (2) –0.5 6.5 V VO Output voltage range (2) –0.5 6.
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TCA6424A www.ti.com SCPS193B – JULY 2010 – REVISED SEPTEMBER 2010 ELECTRICAL CHARACTERISTICS over recommended operating free-air temperature range, VCCI = 1.65 V to 5.5 V (unless otherwise noted) PARAMETER TEST CONDITIONS VCCP MIN –1.2 VIK Input diode clamp voltage II = –18 mA 1.65 V to 5.5 V VPOR Power-on reset voltage VI = VCCP or GND, IO = 0 1.65 V to 5.
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TCA6424A SCPS193B – JULY 2010 – REVISED SEPTEMBER 2010 www.ti.com I2C INTERFACE TIMING REQUIREMENTS over recommended operating free-air temperature range (unless otherwise noted) (see Figure 10) STANDARD MODE I2C BUS MIN MAX 100 FAST MODE I2C BUS UNIT MIN MAX 0 400 fscl I2C clock frequency 0 tsch I2C clock high time 4 0.6 ms tscl I2C clock low time 4.7 1.
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TCA6424A www.ti.
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TCA6424A SCPS193B – JULY 2010 – REVISED SEPTEMBER 2010 www.ti.com TYPICAL CHARACTERISTICS TA = 25°C (unless otherwise noted) SUPPLY CURRENT vs TEMPERATURE 60 VCC = 3.3 V 40 30 VCC = 2.5 V 20 VCC = 1.8 V 10 -15 35 60 5 VCC = 2.5 V 4 3 2 0 1.65 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 85 0 0.1 0.2 0.3 0.4 0.5 50 VCC = 2.5 V 22 20 TA = –40°C TA = 85°C 18 TA = 25°C 16 14 12 10 8 TA = 85°C 6 4 0.2 0.3 0.4 0.
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TCA6424A www.ti.com SCPS193B – JULY 2010 – REVISED SEPTEMBER 2010 TYPICAL CHARACTERISTICS (continued) TA = 25°C (unless otherwise noted) I/O SOURCE CURRENT vs OUTPUT HIGH VOLTAGE I/O SOURCE CURRENT vs OUTPUT HIGH VOLTAGE 50 50 VCC = 2.5 V VCC = 3.3 V 45 Source Current, ISOURCE (mA) TA = –40°C 20 TA = 25°C 15 10 TA = 85°C 5 40 35 TA = 25°C 30 25 20 15 TA = 85°C 10 5 0 0.1 0.2 0.3 0.4 0.5 0.6 0 0.
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TCA6424A SCPS193B – JULY 2010 – REVISED SEPTEMBER 2010 www.ti.com PARAMETER MEASUREMENT INFORMATION VCCI RL = 1 kW SDA DUT CL = 50 pF (see Note A) SDA LOAD CONFIGURATION Two Bytes for READ Input Port Register (see Figure 9) Address Bit 7 (MSB) Stop Start Condition Condition (P) (S) tscl Address Bit 1 R/W Bit 0 (LSB) Data Bit 7 (MSB) ACK (A) Data Bit 0 (LSB) Stop Condition (P) tsch 0.7 ´ VCCI SCL 0.3 ´ VCCI ticr tsp ticf tbuf tvd tvd tocf tsts tsps SDA 0.7 ´ VCCI 0.
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TCA6424A www.ti.com SCPS193B – JULY 2010 – REVISED SEPTEMBER 2010 PARAMETER MEASUREMENT INFORMATION (continued) VCCI RL = 4.7 kW INT DUT CL = 100 pF (see Note A) INTERRUPT LOAD CONFIGURATION ACK From Slave Start Condition 8 Bits (One Data Byte) From Port R/W Slave Address S 0 1 0 0 0 AD 1 DR 1 A 1 2 3 4 5 6 A 7 8 Data 1 ACK From Slave Data From Port Data 2 A 1 P A tir tir B B INT tiv A tsps A Data Into Port Address Data 1 0.5 ´ VCCI INT SCL Data 2 0.
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TCA6424A SCPS193B – JULY 2010 – REVISED SEPTEMBER 2010 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) 500 W Pn DUT 2 ´ VCCP CL = 50 pF (see Note A) 500 W P PORT LOAD CONFIGURATION SCL P0 A P3 0.7 ´ VCCP 0.3 ´ VCCI Slave ACK SDA tpv (see Note B) Pn Unstable Data Last Stable Bit WRITE MODE (R/W = 0) 0.7 ´ VCCI SCL P0 A tps P3 0.3 ´ VCCI tph Pn 0.5 ´ VCCP READ MODE (R/W = 1) A. CL includes probe and jig capacitance. B. tpv is measured from 0.
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TCA6424A www.ti.com SCPS193B – JULY 2010 – REVISED SEPTEMBER 2010 PARAMETER MEASUREMENT INFORMATION (continued) VCCI R L = 1 kW 500 W Pn SDA DUT DUT CL = 50 pF (see Note A) SDA LOAD CONFIGURATION 2 ´ VCCP CL = 50 pF (see Note A) 500 W P PORT LOAD CONFIGURATION Start SCL ACK or Read Cycle SDA 0.3 ´ VCCI tRESET VCCP/2 RESET tREC tREC tW VCCP/2 Pn tRESET A. CL includes probe and jig capacitance. B.
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TCA6424A SCPS193B – JULY 2010 – REVISED SEPTEMBER 2010 www.ti.com APPLICATION INFORMATION Figure 14 shows an application in which the TCA6424A can be used. VCCI VCCP 10 kW (´ 7) VCCI (1.8 V) 10 kW VCC 10 kW 10 kW 31 10 kW 29 SCL Master Controller SDA 30 32 INT GND 29 RESET Status Monitor VCCI SCL 27 VCCP P00 ALARM (see Note D) Subsystem 1 (e.g.
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TCA6424A www.ti.com SCPS193B – JULY 2010 – REVISED SEPTEMBER 2010 Minimizing ICC When I/Os Control LEDs When the I/Os are used to control LEDs, normally they are connected to VCC through a resistor as shown in Figure 14. The LED acts as a diode so, when the LED is off, the I/O VIN is about 1.2 V less than VCC. The ΔICC parameter in Electrical Characteristics shows how ICC increases as VIN becomes lower than VCC.
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TCA6424A SCPS193B – JULY 2010 – REVISED SEPTEMBER 2010 www.ti.com VCC Ramp-Up Ramp-Down VCC_TRR_VPOR50 VIN drops below POR levels Time Time to Re-Ramp VCC_FT VCC_RT Figure 18. VCC is Lowered Below the POR Threshold, Then Ramped Back Up to VCC Table 10 specifies the performance of the power-on reset feature for TCA6424A for both types of power-on reset. Table 10.
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TCA6424A www.ti.com SCPS193B – JULY 2010 – REVISED SEPTEMBER 2010 VCC VPOR VPORF Time POR Time Figure 20.
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TCA6424A SCPS193B – JULY 2010 – REVISED SEPTEMBER 2010 www.ti.com REVISION HISTORY Changes from Original (July 2010) to Revision A • 28 Page Changed Recommended Supply Sequencing and Rates Table ........................................................................................
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PACKAGE OPTION ADDENDUM www.ti.com 20-May-2013 PACKAGING INFORMATION Orderable Device Status (1) TCA6424ARGJR ACTIVE Package Type Package Pins Package Drawing Qty UQFN RGJ 32 3000 Eco Plan Lead/Ball Finish (2) Green (RoHS & no Sb/Br) MSL Peak Temp Op Temp (°C) Device Marking (3) CU NIPDAU Level-1-260C-UNLIM (4/5) -40 to 85 PH424A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device TCA6424ARGJR Package Package Pins Type Drawing UQFN RGJ 32 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 3000 330.0 12.4 Pack Materials-Page 1 5.3 B0 (mm) K0 (mm) P1 (mm) 5.3 0.75 8.0 W Pin1 (mm) Quadrant 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TCA6424ARGJR UQFN RGJ 32 3000 346.0 346.0 35.
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