Datasheet
Table Of Contents
- FEATURES
- DESCRIPTION/ORDERING INFORMATION
- DESCRIPTION/ORDERING INFORMATION (continued)
- Absolute Maximum Ratings
- Recommended Operating Conditions
- Electrical Characteristics
- I2C Interface Timing Requirements
- Switching Characteristics
- TYPICAL CHARACTERISTICS
- PARAMETER MEASUREMENT INFORMATION
- APPLICATION INFORMATION
- REVISION HISTORY
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PW PACKAGE
(TOP VIEW)
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8
16
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9
A0
A1
A2
P0
P1
P2
P3
GND
V
CC
SDA
SCL
INT
P7
P6
P5
P4
TCA9554
www.ti.com
SCPS233A –NOVEMBER 2011–REVISED MARCH 2012
LOW VOLTAGE 8-BIT I
2
C AND SMBus I/O EXPANDER
WITH INTERRUPT OUTPUT AND CONFIGURATION REGISTERS
Check for Samples: TCA9554
1
FEATURES
• I
2
C to Parallel Port Expander • Power-Up With All Channels Configured as
Inputs
• Open-Drain Active-Low Interrupt Output
• No Glitch on Power Up
• Operating Power-Supply Voltage Range of
1.65 V to 5.5 V • Latched Outputs With High-Current Drive
Maximum Capability for Directly Driving LEDs
• 5-V Tolerant I/Os
• Latch-Up Performance Exceeds 100 mA Per
• 400-kHz Fast I
2
C Bus
JESD 78, Class II
• Three Hardware Address Pins Allow up to
• ESD Protection Exceeds JESD 22
Eight Devices on the I
2
C/SMBus
– 2000-V Human-Body Model (A114-A)
• Input/Output Configuration Register
– 200-V Machine Model (A115-A)
• Polarity Inversion Register
– 1000-V Charged-Device Model (C101)
• Internal Power-On Reset
DESCRIPTION/ORDERING INFORMATION
This 8-bit I/O expander for the two-line bidirectional bus (I
2
C) is designed for 1.65-V to 5.5-V V
CC
operation. It
provides general-purpose remote I/O expansion for most microcontroller families via the I
2
C interface [serial clock
(SCL), serial data (SDA)].
The TCA9554 consists of one 8-bit Configuration (input or output selection), Input, Output, and Polarity Inversion
(active high or active low) registers. At power on, the I/Os are configured as inputs with a weak pullup to V
CC
.
However, the system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration
bits. The data for each input or output is kept in the corresponding Input or Output register. The polarity of the
Input Port register can be inverted with the Polarity Inversion register. All registers can be read by the system
master.
The system master can reset the TCA9554 in the event of a timeout or other improper operation by utilizing the
power-on reset feature, which puts the registers in their default state and initializes the I
2
C/SMBus state machine.
The TCA9554 open-drain interrupt (INT) output is activated when any input state differs from its corresponding
Input Port register state and is used to indicate to the system master that an input state has changed.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2011–2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.