) Data Manual 1996 Mixed-Signal Products
Printed in U.S.A.
TCM4300 Data Manual Advanced RF Cellular Telephone Interface Circuit (ARCTIC ) SLWS010F October 1996 Printed on Recycled Paper
IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. TI warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with TI’s standard warranty.
Contents Section 1 2 3 Title Page Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1 1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1 1.2 TCM4300 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 1.3 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9 TCM4300 to Microcontroller Interface Timing Requirements (Motorola 8-Bit Write Cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–9 3.10 Switching Characteristics, TCM4300 to DSP Interface (Read Cycle) . . . . . . . . . 3–10 3.11 Switching Characteristics, TCM4300 to DSP Interface (Write Cycle) . . . . . . . . . 3–11 4 Principles of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.
List of Illustrations Figure Title Page 3–1 3–10 3–11 MCLKOUT Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Microcontroller Interface Timing Requirements (Mitsubishi Configuration Read Cycle, MTS [1:0] = 10) . . . . . . . . . . . . . . . . . . . . . . Microcontroller Interface Timing Requirements (Mitsubishi Configuration Write Cycle, MTS [1:0] = 10) . . . . . . . . . . . . . . . . . . . . . .
List of Tables Table Title Page 4–1 4–2 4–3 4–4 4–5 4–6 4–7 4–8 4–9 4–10 4–11 4–12 4–13 4–14 4–15 4–16 4–17 4–18 4–19 4–20 4–21 4–22 4–23 4–24 4–25 4–26 4–27 4–28 TCM4300 Receive Channel Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RXIP, RXIN, RXQP, and RXQN Inputs (AVDD = 3 V, 4.5 V, 5 V) . . . . . . . . . . . . . . Receive (RX) Channel Frequency Response (FM Input in Analog Mode) . . . . . . Receive (RX) Channel Frequency Response (RXI, RXQ Input in Digital Mode) .
1 Introduction Texas Instruments (TI) TCM4300 IS-54B advanced RF cellular telephone interface circuit (ARCTIC) provides a baseband interface between the digital signal processor (DSP), the microcontroller, and the RF modulator/demodulator in a dual-mode IS-54B cellular telephone. See the TCM4300 functional block diagram. In the analog mode, the TCM4300 provides all required baseband filtering as well as transmit D/A conversion and receive A/D conversion using dual 10-bit sigma-delta converters.
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1.4 Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION AFC 11 O Automatic frequency control. The AFC DAC output provides the means to adjust system temperature-compensated reference oscillator (TCXO). AGC 10 O Automatic gain control. The AGC digital-to-analog converter (DAC) output can be used to control the gain of system receiver circuits. AVDDREF 3 — Analog supply voltage for FM receive path. Power applied to AVDDREF powers the FM receive path circuitry.
1.4 Terminal Functions (Continued) TERMINAL NAME NO. I/O DESCRIPTION DSPRW 69 I DSP read/write. A high on DSPRW enables a read operation and a low enables a write operation to the DSP. DSPSTRBL 68 I DSP strobe low. The DSPSTRL (active low) is used in conjunction with DSPCSL to enable read/write operations to the DSP. DVDD 35, 45, 63, 75, 90 — Digital power supply. All supply terminals must be connected together. DVSS 34, 46, 65, 76, 91 — Digital ground.
1.4 Terminal Functions (Continued) TERMINAL NAME NO. I/O DESCRIPTION MCDS 48 I Microcontroller data strobe. MCDS is configured by the signals present on MTS0 and MTS1. MCLKIN 64 I Master clock input. The MCLKIN frequency input requirement is 38.88 MHz ± 100 ppm. A crystal can be connected between MCLKIN and XTAL to provide an oscillator circuit. As an alternative, XTAL can be left open and an external TTL /CMOS-level clock signal can be connected to MCLKIN.
1.4 Terminal Functions (Continued) TERMINAL NAME NO. I/O DESCRIPTION SCEN 94 O Speech CODEC enable. A high out from SCEN can enable the speech CODEC. SINT 79 O Sample interrupt. SINT is active low. In the analog mode, SINT occurs at 40 kHz; in the digital mode, SINT occurs at 48.6 kHz. SYNCLK 32 O Synthesizer clock. SYNCLK clocks the serial data stream. SYNDTA 31 O Synthesizer serial-data. SYNDTA provides the serial bit stream output.
2 Electrical Specifications This section lists the electrical specifications, the absolute maximum ratings, the recommended operating conditions and operating characteristics for the TCM4300 Advanced RF Cellular Telephone Interface Circuit. 2.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range (unless otherwise noted)† Supply voltage range: DVDD (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . VSS – 0.3 V to AVDD +0.3 V AVDD (see Notes 2 and 3) . . . . . . . . . . . . . . .
2.3 Recommended Operating Conditions MIN Supply voltage, DVDD NOM MAX UNIT 5.5 V DVDD+0.3 V 0.3 DVDD V DVDD V 3 High-level input voltage, VIH Digital Low-level input voltage, VIL Digital 0.
2.4.3 Terminal Impedance MIN TYP† Receive channel input impedance (single ended), RXIP/N and RXQP/N 40 70 Transmit channel output impedance (single ended), TXIP/N and TXQP/N 40 50 FM input impedance, WBD 25 200 FUNCTION MCLKOUT impedance MCLKOUT at 3.3 V 240 MCLKOUT at 5 V 180 MAX UNIT kΩ Ω 100 kΩ Ω † All typical values are at DVDD = 5 V, AVDD = 5 V, and TA = 25°C, unless otherwise specified. 2.4.4 RXIP, RXIN, RXQP, and RXQN Inputs (AVDD = 3 V, 4.
2.4.5 Transmit I and Q Channel Outputs PARAMETER MIN Peak output voltage full scale scale, centered at VCM Nominal output output-level level (constellation radius) centered at VCM TYP Differential 2.24 Single ended 1.12 Differential MAX UNIT Vp 1.5 Single ended V 0.75 ± 200 Low-level drift Transmit error vector magnitude (EVM) 3% Resolution PPM/°C 4% 8 S/(N+D) ratio at differential outputs 48 bits 52 ± 8% Gain error (I or Q channel) dB ± 12% ± 0.
2.4.7 Auxiliary D /A Converters Slope (AGC, AFC, PWRCONT) AUXFS[1:0] SETTING SLOPE NOMINAL LSB VALUE (V) NOMINAL OUTPUT VOLTAGE FOR DIGITAL CODE = 128 (MIDRANGE) (V) NOMINAL OUTPUT VOLTAGE FOR DIGITAL CODE = 256† (MAX VALUE) (V) 00 2.5/256 0.0098 1.25 2.5 01 Do not use Do not use Do not use Do not use 10 4/256 0.0156 2 4 11 4.5/256 0.0176 2.25 4.5 † The maximum input code is 255. The value shown for 256 is extrapolated. 2.4.
2.5 Operating Characteristics Over Full Range of Operating Conditions (Unless Otherwise Noted) 2.5.1 Receive (RX) Channel Frequency Response (RXI, RXQ Input in Digital Mode) PARAMETER TEST CONDITIONS MIN 0.125 V peak-to-peak, 0 kHz to 8 kHz (see Note 4) 0.125 V peak-to-peak, 8 kHz to 15 kHz (see Note 5) 0.125 V peak-to-peak, 16.2 kHz to 18 kHz (see Note 5) – 26 0.125 V peak-to-peak, 18 kHz to 45 kHz (see Note 5) – 30 0.125 V peak-to-peak, 45 kHz to 75 kHz (see Note 5) – 46 0.
2.5.4 Transmit (TX) Channel Frequency Response (Analog Mode) PARAMETER TEST CONDITIONS MIN TYP 20 kHz to 45 kHz (see Note 5) – 31 45 kHz to 75 kHz (see Note 5) – 70 > 75 kHz (see Note 5) – 70 Any 30 kHz band centered at > 90 kHz (see Note 5) – 70 Peak-to-peak group delay distortion 0 kHz to 15 kHz Absolute channel delay 0 kHz to 15 kHz UNIT ± 0.5 8 kHz to 15 kHz (see Note 4) F Frequency response MAX ± 0.5 0 kHz to 8 kHz (see Note 4) dB 3 540 µs µs NOTES: 4. Ripple magnitude 5.
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3 Parameter Measurement Information This section contains the timing waveforms and parameter values for MCLKOUT and several microcontroller interface configurations possible when using the TCM4300. The timing parameters are contained in Section 3.1 through Section 3.11. The timing waveforms are shown in Figures 3–1 through 3–11. All parameters shown in the separate waveforms have their values listed in an associated table.
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4 Principles of Operation This section describes the operation of the TCM4300 in detail. NOTE: Timing diagrams and associated tables are contained in Section 3 of this data manual. 4.1 Data Transfer The interface to both the system digital signal processor and microcontroller is in the form of 2s complement. 4.2 Receive Section The mode of operation is determined by the state of the MODE, FMVOX, IQRXEN, and FMRXEN bits of the DStatCtrl register, as shown in Table 4–1. Table 4–1.
Table 4–2. RXIP, RXIN, RXQP, and RXQN Inputs (AVDD = 3 V, 4.5 V, 5 V) PARAMETER TEST CONDITIONS Input voltage range Input voltage for full full- scale digital output Nominal operating level MIN TYP 0.3 Differential 0.5 Single ended 0.5 Differential 0.125 Single ended 0.125 Input CMRR (RXI, RXQ) UNIT V Vp-p Vp-p Vp p† 45 dB Sampling frequency, SINT (digital mode) 48.6 Sampling frequency, SINT (analog mode) 40 Receive error vector magnitude (EVM) I/Q sample timing skew MAX AVDD– 0.
Table 4–3. Receive (RX) Channel Frequency Response (FM Input in Analog Mode) PARAMETER TEST CONDITIONS MIN TYP Frequency y response p F q 2.5 peak-to-peak p k 25Vp k 20 kHz to 30 kHz (see Note 2) – 18 34 kHz to 46 kHz (see Note 3) – 48 Peak-to-peak group delay distortion 2.5 V peak-to-peak, 0 kHz to 6 kHz Absolute channel delay 2.5 V peak-to-peak, 0 kHz to 6 kHz MAX UNIT ± 0.5 0 kHz to 6 kHz (see Note 1) dB 2 µs µs 400 NOTES: 1. Ripple magnitude 2. Stopband 3.
square-root raised-cosine (SQRC) shaping filter with a roll-off rate of α = 0.35 and converted to sampled analog form by two 9-bit digital-to-analog converters (DACs). The output of the DAC is then filtered by a continuous-time resistance-capacitance (RC) filter. The TCM4300 generates a power amplifier (PA) control signal, PAEN, to enable the power supply for the PA. The start and stop times of the TDM burst are controlled by writing to a single bit, TXGO, in the DSP DStatCtrl register.
Table 4–6. Transmit (TX) Channel Frequency Response (Digital Mode) PARAMETER F Frequency response TEST CONDITIONS MIN TYP MAX 0 kHz to 8 kHz (see Note 4) ± 0.3 8 kHz to 15 kHz (see Note 4) ± 0.5 20 kHz to 45 kHz (see Note 2) – 29 45 kHz to 75 kHz (see Note 2) – 55 > 75 kHz (see Note 2) – 60 Any 30 kHz band centered at > 90 kHz (see Note 2) – 60 Peak-to-peak group delay distortion 0 kHz to 15 kHz Absolute channel delay 0 kHz to 15 kHz UNIT dB 3 µs µs 320 NOTES: 2. Stopband 4.
delay after the last symbol occurs (2 SINT periods before TXGO goes low); then the transmit outputs decay to zero differential voltage (each output at the voltage supplied to the VCM input terminal). The shape of the decay is the transient resulting from the internal SQRC filtering. The transmit outputs are held at zero differential voltage 6 SINT periods (3 symbol periods) after the start of the decay. At this time the PAEN digital output is set low (see Figure 4–1 and Figure 4–2).
Dibit In D Q CLK TXGO D Q BST Offset Delay Channel Delay (15.5 SINT Periods) Delay = 0, 1/4, 1/2, 3/4 BST Offset Delay SINT Transmit Channel Delay + d(T/8) Occurs from last symbol (2 SINT periods) before TXGO goes low PAEN Delay 9.5 CLK SYNOL TXI, TXQ PAEN 19.5 MPAEN PAEN Delay + d(T/8) TXGO high: 9.5 SINT periods + d(T/8): PAEN high TXGO low: 19.5 SINT periods + d(T/8): PAEN low Figure 4–2. Transmit Power Ramp-Up/Ramp-Down Functional Diagram 4.
Table 4–8. Typical Bit-Error-Rate Performance (WBD_BW = 000) PARAMETER TEST CONDITIONS MEAN CNR MIN MAX –5 Bit Bi error rate UNIT 0.4 0 0.279 5 0.143 10 0.056 15 0.0192 20 0.00623 25 0.00199 dB The WBDD is controlled by the bits in the control register WBDCtrl (see Table 4–9). Table 4–9.
At the same time, the interrupts DWBDINT and MWBDFINT are asserted. The interrupt rate is 800 µs (8 bits/10 kHz). These interrupts are individually cleared when the WBD register is read by the corresponding processor. They can also be cleared by their respective processor by writing a 1 to the corresponding clear WBD bit. There is one WBD control register. It can be written to by either processor port. 4.
4.9 Auxiliary DACs, LCD Contrast Converter Auxiliary DACs generate AFC, AGC and power control signals for the RF system. These three D/A converters are updated when the corresponding data is received from the DSP. In fewer than 5 µs after the corresponding registers are written to, the output has settled to within 1 LSB of its new value (see Table 4–10). Table 4–10. Auxiliary D/A Converters PARAMETER TEST CONDITIONS AVDD > 3 V†, AUXFS [1:0] = 00 AVDD > 4.
4.9 Auxiliary DACs, LCD Contrast Converter (continued) Table 4–12. Auxiliary D /A Converters Slope (LCDCONTR) SLOPE NOMINAL LSB VALUE (V) NOMINAL OUTPUT VOLTAGE FOR DIGITAL CODE = 8 (MIDRANGE) (V) NOMINAL OUTPUT VOLTAGE FOR DIGITAL CODE = 16† (MAX VALUE) (V) 00 2.5/16 0.1563 1.25 2.5 01 Do not use Do not use Do not use Do not use 10 4/16 0.2500 2 4 11 4.5/16 0.2813 2.25 4.5 AUXFS[1:0] SETTING † The maximum input code is 15. The value shown for 16 is extrapolated. 4.
Codec Master Clock 2.048 MHz CMCLK Codec Sample Clock 8 kHz CSCLK Figure 4–4. Codec Master and Sample Clock Timing 4.11.1 Clock Generation There are three options for generating the master clock. A fundamental crystal or a third-overtone crystal with a frequency of 38.88 MHz can be connected between the MCLKIN and the XTAL terminals or an external clock source can be connected directly to the MCLKIN terminal. The MCLKOUT is a buffered master clock output at the same frequency as MCLKIN.
4.11.5 Phase-Adjustment Strategy For an IS-54 system in the digital mode, receiver sample timing must be phase adjusted to synchronize the A/D conversions to optimum sampling points of the received symbols, and to synchronize the mobile unit timing to the base station timing. This is done by temporarily increasing or decreasing the periods of the clocks to be adjusted. To avoid undesirable transients, each cycle of the clock being adjusted is altered by only one period of MCLKIN.
2.048-MHz Codec Master Clock CMCLK ÷ 17, 18, 19, 20 ÷ 256 =0 Bits 0 – 5 Adjust Counter B From DSP RCO 8-kHz Codec Sample Clock CSCLK 10 Phase-Adjusted 9.72-MHz Clock Adjust Counter A 38.88 MHz MCLKIN ÷ 243/ ÷ 200 ÷ 3, 4, 5 Analog/Digital 40.0/48.6-kHz A/ D Sample Clock (SINT) Analog/Digital Mode (MODE bit) Frequency Synth. Clock 303.75 kHz From Microcontroller Clock Divider Chain 5 ÷N WBD Demod. 6.48 MHz ADC Clocks DAC Clocks Microcontroller Clock MCCLK N = (2, 3, . . . 32) MCLKEN Sync.
4.12 Frequency Synthesizer Interface The synthesizer interface provides a means of programming three synthesizers. The synthesizer-side outputs are a data line, a clock line, and three latch enable lines that separately strobe data into each synthesizer. The control inputs are registers mapped into the microcontroller address space. The status of the interface can be monitored to determine when the programming operation has been completed. The synthesizer interface is designed to be general purpose.
CLKPOL 5 NUMCLKS 5 LOWVAL 5 HIGHVAL Ready and Timing Logic Control Registers 3 SEL[2:0] MSB/LSB FIRST SYNRDY To MStatCtrl Register SYNDTA M U X D SYNLE0 Q E 32 32-Bit Data Register 8 µC Bus SEL 0 5 D SYNLE1 DMUX Q E A SEL 1 S D SYNLE2 Q Q HIGHVAL A=B B R E A A=B SEL 2 CLKPOL SYNCLK Clock Circuit LOWVAL 5 B A B≤A B NUMCLKS BIT CNT [0 . . . 31] Figure 4–6. Synthesizer Interface Circuit Block Diagram 4–16 MSB/LSB FIRST 303.
The SynData0 register contains the least significant bits of the 32-bit data register. SynData3 contains the most significant bits. The bits in the SynCtrl0, SynCtrl1, and SynCtrl2 registers are allocated as shown in Figure 4–7. SynCtrl0 SynCtrl1 S C l1 SynCtrl2 7–5 4–0 SEL[2:0] LOWVAL 7–6 5 4–0 Reserved MSB/LSB FIRST HIGHVAL 7–6 5 4–0 Reserved CLKPOL NUMCLKS Figure 4–7. Contents of SynData Registers Table 4–14 identifies the meaning of each of the bit fields in SynCtrl[2:0]. Table 4–14.
Up to 31 data bits plus a latch enable (SYNLE0,1,2) can be programmed in one programming cycle. When data greater than or equal to 32 bits must be programmed, TI recommends using two or more programming cycles with data in each cycle and a latch enable in the final programming cycle. Two or more programming cycles are recommended because all programming cycles must contain at least one SYNCLK pulse, whereas the latch enable can be suppressed in any programming cycle.
In addition to allowing control of power to external functional modules, these power control bits combined with other control bits are used to control internal TCM4300 functions. This control system is shown in Figure 4–9.
In the analog mode, (MODE bit set low), PAEN is high whenever TXEN is active and SYNOL is low. The SYNOL input can be used as an indication to the TCM4300 that the external synthesizers are out of lock. The PAEN signal is gated by SYNOL to prevent off-channel transmissions. The TXEN, IQRXEN, FMVOX, and MODE signals are generated by sampling the corresponding bits of the DStatCtrl register with the internal SINT.
4.15 Microcontroller Register Map The microcontroller can access 17 locations within the TCM4300. The register locations are 8 bits wide as shown in Table 4–16 and Table 4–17. Table 4–16.
Table 4–17.
Table 4–18. WBDCtrl Register BIT R/W NAME FUNCTION RESET VALUE 0 9 R/W WBD_LCKD Wide-band data lock data. WBD_LCKD determines whether edge detector is locked (1) or unlocked (0). 8 R/W WBD_ON Wide-band data on. WBD_ON turns the WBDD module on/off (1/0). 0 7–5 R/W WBD_BW[2:0] Wide-band data bandwidth. WBD_BW[2:0] sets the appropriate PLL bandwidth. 000 : 20 Hz 001 : 39 Hz 010 : 78 Hz 011 : 156 Hz 100 : 313 Hz 101 : 625 Hz 110 : 1250 Hz 110 4–0 — — Reserved — 4.
Table 4–19. MStatCtrl Register Bits BIT R/W NAME FUNCTION RESET VALUE Level on SYNOL input terminals 7 R SYNOL Synthesizer out of lock. SYNOL is equal to the level applied to SYNOL input pin. SYNOL can be used as an input for an externally generated status signal to prevent transmission when external synthesizers are out of lock. In digital mode, when SYNOL is high, PAEN is not asserted and no signal can be transmitted from TXIP, TXIN, TXQP, and TXQN. 6 R TXONIND Transmitter on indicator.
4.19 DSP Register Map The register map accessible to the DSP port is shown in Table 4–20 and Table 4–21. There are 14 system addressable locations. Note that the write address of FIFO B is the same as the read address of FIFO A. Figure 4-11 details the connection of TCM4300 to an example DSP. Table 4–20.
10 DSPD[9:0] D[15:6] 4 DSPA[3:0] A[3:0] DSPCSL IS DSPRW TCM4300 R/W DSPSTRBL STRB SINT INT 1 CINT INT 3 BDINT INT 4 DSP Figure 4–11. DSP Interface 4.20 Wide-Band Data Registers Bit 9 of the wide-band data register is the most recently received bit as shown below. WBD 9–2 1–0 WB Data Reserved R WBDCtrl WBDC l 9 8 7–5 4–0 WBD_LCKD WBD_ON WBD_BW Reserved R/W 4.
4.22 DSP Status and Control Registers DIntCtrl, Clear and Send Bits: The bit names in the DIntCtrl register indicate the action to be taken when a 1 is written to the respective bit. When these bits are being read, a 1 indicates that the corresponding interrupt is pending. A 0 indicates that the interrupt is not pending. Writing a 0 to any bit has no effect. Writing a 1 to the clear bits clears the corresponding interrupt, and the interrupt terminal returns to its inactive level.
4.23 Reset A low on RSINL causes the TCM4300 internal registers to assume their reset values. The power-on reset circuit also causes internal reset. However, the logic level at RSINL has no effect on reset outputs RSOUTH and RSOUTL. The effects of resetting the TCM4300 are described in the following paragraphs. 4.23.1 Power-On Reset The power-on reset (POR) is digitally implemented and provides a timed POR signal at RSOUTL and RSOUTH. The POR pulse duration is equal to 388,800 cycles of MCLKIN (10 ms).
4.24 Microcontroller Interface The microcontroller interface of the TCM4300 is a general purpose bus interface (see Table 4–24) which ensures compatibility with a wide range of microcontrollers, including the Mitsubshi M37700 series and most Intel and Motorola series.
4.24.2 Mitsubishi Microcontroller Mode of Operation When the microcontroller type select MTS1 and MTS0 inputs are held high and low, respectively, the TCM4300 microcontroller interface is configured in Mitsubishi mode. In this mode, the interface has a single read/write control (R / W) signal, an active-low data strobe (MCDS) signal, and active-low interrupt request signals. The processor E and R/(W) signals should be connected to the TCM4300 MCDS signal and the MCRW signal, respectively.
Table 4–28.
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5 Mechanical Data 5.1 PZ (S-PQFP-G100) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 75 0,08 M 51 76 50 100 26 0,13 NOM 1 25 12,00 TYP 14,20 SQ 13,80 Gage Plane 16,20 SQ 15,80 0,05 MIN 1,45 1,35 0,25 0°– 7° ā 0,75 0,45 Seating Plane 1,60 MAX 0,08 4040149 / A 03/95 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. TI warrants performance of its semiconductor products and related software to the specifications applicable at the time of sale in accordance with TI’s standard warranty.
