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TFP401A-EP

www.ti.com

SLDS160A –MARCH 2009– REVISED JULY 2011

TI PanelBus™ DIGITAL RECEIVER

Check for Samples: TFP401A-EP

FEATURES

SUPPORTS DEFENSE, AEROSPACE,

AND MEDICAL APPLICATIONS

• Supports Pixel Rates Up to 165 MHz (including

1080p and WUXGA at 60Hz)

• Controlled Baseline

• Digital Visual Interface (DVI) Specification

• One Assembly/Test Site

Compliant

(1)

• One Fabrication Site

• True-Color, 24 Bit/Pixel, 16.7M Colors at One

• Available in Military (–55°C/125°C)

or Two Pixels Per Clock

Temperature Range (Custom temperature

• Laser Trimmed Internal Termination Resistors

ranges available)

for Optimum Fixed Impedance Matching

• Extended Product Life Cycle

• Skew Tolerant Up to One Pixel Clock Cycle

• Extended Product-Change Notification

• 4x Over-Sampling

• Product Traceability

• Reduced Power Consumption - 1.8 V Core

Operation With 3.3 V I/Os and Supplies

(2)

DESCRIPTION

• Reduced Ground Bounce Using

The Texas Instruments TFP401A is a TI PanelBus ™

Time-Staggered Pixel Outputs

flat panel display product, part of a comprehensive

• Low Noise and Power Dissipation Using TI

family of end-to-end DVI 1.0 compliant solutions.

PowerPAD™ Packaging

Targeted primarily at desktop LCD monitors and

digital projectors, the TFP401A finds applications in

• Advanced Technology Using TI 0.18-mm

any design requiring high-speed digital interface. The

EPIC-5™ CMOS Process

TFP401A supports display resolutions up to 1080p

• TFP401A Incorporates HSYNC Jitter

and WUXGA in 24-bit true color pixel format. The

Immunity

(3)

TFP401A offers design flexibility to drive one or two

pixels per clock, supports TFT or DSTN panels, and

provides an option for time staggered pixel outputs

for reduced ground bounce. PowerPAD™ advanced

packaging technology results in best of class power

(1) The Digital Visual Interface Specification, DVI, is an industry

dissipation, footprint, and ultra-low ground

standard developed by the Digital Display Working Group

inductance. The TFP401A combines PanelBus ™

(DDWG) for high-speed digital connection to digital displays.

circuit innovation with TI's advanced 0.18-mm

The TFP401A is compliant to the DVI Specification Rev. 1.0.

(2) The TFP401A has an internal voltage regulator that provides EPIC-5™ CMOS process technology, along with TI

the 1.8-V core power supply from the externally supplied

PowerPAD™ package technology to achieve a

3.3-V supplies.

reliable, low-powered, low-noise, high-speed digital

(3) The TFP401A incorporates additional circuitry to create a

interface solution.

stable HSYNC from DVI transmitters that introduce

undesirable jitter on the transmitted HSYNC signal.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PanelBus, PowerPAD, EPIC-5 are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (23 pages)

PAGE 1
TFP401A-EP SLDS160A – MARCH 2009 – REVISED JULY 2011 www.ti.com TI PanelBus™ DIGITAL RECEIVER Check for Samples: TFP401A-EP FEATURES 1 • 2 • • • • • • • • • • (1) (2) (3) Supports Pixel Rates Up to 165 MHz (including 1080p and WUXGA at 60Hz) Digital Visual Interface (DVI) Specification Compliant (1) True-Color, 24 Bit/Pixel, 16.
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TFP401A-EP SLDS160A – MARCH 2009 – REVISED JULY 2011 www.ti.com ORDERING INFORMATION (1) PACKAGED DEVICE (2) (1) (2) TA 100-TQFP (PZP) –55°C to 125°C TFP401AMPZPEP For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com. Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package.
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TFP401A-EP SLDS160A – MARCH 2009 – REVISED JULY 2011 www.ti.com FUNCTIONAL BLOCK DIAGRAM 3.3 V 3.3 V 1.8 V Regulator Internal 50-Ω Termination 3.
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TFP401A-EP SLDS160A – MARCH 2009 – REVISED JULY 2011 www.ti.com TERMINAL FUNCTIONS (continued) TERMINAL NAME PD NO. 2 I/O DESCRIPTION DI Power down - An active low signal that controls the TFP401A power-down state. During power down all output buffers are switched to a high impedance state. All analog circuits are powered down and all inputs are disabled, except for PD. If PD is left unconnected an internal pullup defaults the TFP401A to normal operation.
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TFP401A-EP SLDS160A – MARCH 2009 – REVISED JULY 2011 www.ti.com TERMINAL FUNCTIONS (continued) TERMINAL NAME NO. I/O DESCRIPTION Rx0- 91 AI Channel-0 negative receiver input - Negative side of channel-0. TMDS low voltage signal differential input pair. Rx1+ 85 AI Channel-1 positive receiver input - Positive side of channel-1 TMDS low voltage signal differential input pair. Channel-1 receives green pixel data in active display and CTL1 control signals in blank.
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TFP401A-EP SLDS160A – MARCH 2009 – REVISED JULY 2011 www.ti.com RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) VDD (DVDD, AVDD, PVDD, OVDD) Supply voltage tpix (1) Pixel time NOM MAX 3 3.3 3.6 V 40 ns 6.06 Rt Single ended analog input termination resistance TA Operating free-air temperature (1) MIN 45 50 -55 UNIT 57 Ω 125 °C tpix is the pixel time defined as the period of the RxC clock input.
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TFP401A-EP SLDS160A – MARCH 2009 – REVISED JULY 2011 www.ti.
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TFP401A-EP SLDS160A – MARCH 2009 – REVISED JULY 2011 www.ti.
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TFP401A-EP SLDS160A – MARCH 2009 – REVISED JULY 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION tr1 tf1 80% QE(0-23), QO(0-23), DE CTK(1-3), HSYNC, VSYNC 80% 20% 20% Figure 1. Rise and Fall TIme of Data and Control Signals tr2 tf2 80% ODCK 80% 20% 20% Figure 2. Rise and Fall Time of ODCK fODCK ODCK Figure 3. ODCK Frequency t(su2) t(su1) t(h2) t(h1) VOH VOL ODCK VOH VOL QE(0-23), QO(0-23), DE CTL(1-3), HSYNC, VSYNC VOH VOL VOH VOL VOH VOL VOH VOL OCK_INV Figure 4.
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TFP401A-EP SLDS160A – MARCH 2009 – REVISED JULY 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) PDO VIL tpd(PDOL) QE(0-23), QO(0-23), ODCK, DE, CTL(2-3), HSYNC, VSYNC Figure 8. Delay from PDO Low to Hi-Z Outputs VIH PD tp(PDH-V) DFO, ST, PIXS, STAG, Rx(0-2)+, Rx(0-2)-, OCK_INV Figure 9. Delay from PD Low to High Before Inputs are Active twL(PDL_MIN) VIL PD Figure 10. Minimum Time PD Low TX2 50% TX1 tccs TX0 50% Figure 11.
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TFP401A-EP SLDS160A – MARCH 2009 – REVISED JULY 2011 www.ti.com FUNDAMENTAL OPERATION The TFP401A is a digital visual interface (DVI) compliant TMDS digital receiver that is used in digital flat panel display systems to receive and decode TMDS encoded RGB pixel data streams.
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TFP401A-EP SLDS160A – MARCH 2009 – REVISED JULY 2011 www.ti.com TFP401A CLOCKING AND DATA SYNCHRONIZATION The TFP401A receives a clock reference from the DVI transmitter that has a period equal to the pixel time, Tpix. The frequency of this clock is also referred to as the pixel rate. Since the TMDS encoded data on Rx[2:0] contains 10 bits per 8-bit pixel, it follows that the Rx[2:0] serial bit rate is 10 times the pixel rate.
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TFP401A-EP SLDS160A – MARCH 2009 – REVISED JULY 2011 www.ti.com DVI Transmitter TI TFP401/401A Receiver AVDD DVI Compliant Cable Internal Termination at 50 Ω DATA DATA + _ Current Source Figure 14. TMDS Differential Input and Transmitter Connection 1/2 VIDIFF AVCC AVCC - 1/2 VIDIFF a ) Single-Ended Input Signal VIDIFF + 1/2 VIDIFF - 1/2 VIDIFF b) Differential Input Signal Figure 15.
PAGE 14
TFP401A-EP SLDS160A – MARCH 2009 – REVISED JULY 2011 www.ti.com This HSYNC regeneration circuit is transparent to the monitor and need not be removed even if the transmitted HSYNC is stable. For example, the PanelBus ™ line of DVI 1.0 compliant transmitters, such as the TFP6422 and TFP420, do not have the HSYNC jitter problem. The TFP401A will operate correctly with either compliant or noncompliant transmitters.
PAGE 15
TFP401A-EP www.ti.com SLDS160A – MARCH 2009 – REVISED JULY 2011 Time Staggered Pixel Output. This option works only in conjunction with the 2-pixel/clock mode (PIXS = high). Setting STAG = low will time stagger the even and odd pixel output so as to reduce the amount of instantaneous current surge from the power supply. Depending on the PCB layout and design this can help reduce the amount of system ground bounce and power supply noise.
PAGE 16
TFP401A-EP SLDS160A – MARCH 2009 – REVISED JULY 2011 www.ti.com Soldering the back side pad of the device to a thermal land connected to the PCB ground plane is recommended for electrical and EMI considerations. The thermal land may be soldered to the exposed PowerPAD™ using standard reflow soldering techniques. The recommended pad size for the grounded thermal land is 5.6mm sq. minimum, centered in the device land pattern.
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TFP401A-EP SLDS160A – MARCH 2009 – REVISED JULY 2011 www.ti.com REVISTION HISTORY Changes from Original (March 2009) to Revision A Page • Changed 1st bullet in FEATURES: FROM: Supports UXGA Resolution (Output Pixel Rate Up to 165MHz) TO: Supports Pixel Rates Up to 165 MHz (including 1080p and WUXGA at 60Hz) ................................................................... 1 • Changed sentence in first paragraph of description FROM: supports display resolutions up to UXGA in 24-bit true color pixel.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.