Information

ManualsBrandsTEXAS INSTRUMENTS ManualsInterface ICsInterface IC - receivers DVI 0/1 HTQFP 100

TFP401

TFP401A

www.ti.com

SLDS120E –MARCH 2000–REVISED JULY 2013

TI PanelBus ™ DIGITAL RECEIVER

Check for Samples: TFP401, TFP401A

FEATURES

DESCRIPTION

The Texas Instruments TFP401 and TFP401A are TI

• Supports Pixel Rates Up to 165 MHz (Including

PanelBus™ flat-panel display products, part of a

1080p and WUXGA at 60 Hz)

comprehensive family of end-to-end DVI 1.0

• Digital Visual Interface (DVI) Specification

compliant solutions. Targeted primarily at desktop

Compliant

(1)

LCD monitors and digital projectors, the

TFP401/401A finds applications in any design

• True-Color, 24-Bit/Pixel, 16.7M Colors at 1 or 2

requiring high-speed digital interface.

Pixels per Clock

• Laser Trimmed Internal Termination Resistors

The TFP401/401A supports display resolutions up to

for Optimum Fixed Impedance Matching 1080p and WUXGA in 24-bit true-color pixel format.

The TFP401/401A offers design flexibility to drive one

• Skew Tolerant Up to One Pixel-Clock Cycle

or two pixels per clock, supports TFT or DSTN

• 4× Oversampling

panels, and provides an option for time-staggered

• Reduced Power Consumption – 1.8-V Core

pixel outputs for reduced ground bounce.

Operation With 3.3-V I/Os and Supplies

(2)

PowerPAD advanced packaging technology results in

• Reduced Ground Bounce Using Time-

best-of-class power dissipation, footprint, and ultralow

Staggered Pixel Outputs

ground inductance.

• Low Noise and Good Power Dissipation Using

The TFP401/401A combines PanelBus circuit

TI PowerPAD™ Packaging

innovation with TI's advanced 0.18-µm EPIC-5™

CMOS process technology, along with TI PowerPAD

• Advanced Technology Using TI 0.18-µm EPIC-

package technology to achieve a reliable, low-

5™ CMOS Process

powered, low-noise, high-speed digital interface

• TFP401A Incorporates HSYNC Jitter

solution.

Immunity

(3)

(1) The Digital Visual Interface Specification, DVI, is an industry

AVAILABLE OPTIONS

standard developed by the Digital Display Working Group

PACKAGED DEVICE

(DDWG) for high-speed digital connection to digital displays.

The TPF401 and TFP401A are compliant with the DVI

100-TQFP (PZP)

Specification Rev. 1.0.

TFP401PZP

(2) The TFP401/401A has an internal voltage regulator that

0°C to 70°C

provides the 1.8-V core power supply from the external 3.3-V

TFP401APZP

supplies.

(3) The TFP401A incorporates additional circuitry to create a

stable HSYNC from DVI transmitters that introduce

undesirable jitter on the transmitted HSYNC signal.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PanelBus, PowerPAD, EPIC-5 are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (21 pages)

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TFP401 TFP401A www.ti.com SLDS120E – MARCH 2000 – REVISED JULY 2013 TI PanelBus ™ DIGITAL RECEIVER Check for Samples: TFP401, TFP401A FEATURES DESCRIPTION • Supports Pixel Rates Up to 165 MHz (Including 1080p and WUXGA at 60 Hz) Digital Visual Interface (DVI) Specification Compliant (1) True-Color, 24-Bit/Pixel, 16.
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TFP401 TFP401A SLDS120E – MARCH 2000 – REVISED JULY 2013 www.ti.
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TFP401 TFP401A www.ti.com SLDS120E – MARCH 2000 – REVISED JULY 2013 FUNCTIONAL BLOCK DIAGRAM 3.3 V 3.3 V 1.8 V Regulator Internal 50-Ω Termination 3.
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TFP401 TFP401A SLDS120E – MARCH 2000 – REVISED JULY 2013 www.ti.com TERMINAL FUNCTIONS (continued) TERMINAL NAME NO. PD 2 I/O DESCRIPTION DI Power down – An active-low signal that controls the TFP401/401A power-down state. During power down, all output buffers are switched to a high-impedance state. All analog circuits are powered down and all inputs are disabled, except for PD. If PD is left unconnected, an internal pullup defaults the TFP401/401A to normal operation.
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TFP401 TFP401A www.ti.com SLDS120E – MARCH 2000 – REVISED JULY 2013 TERMINAL FUNCTIONS (continued) TERMINAL I/O DESCRIPTION 85 AI Channel-1 positive receiver input – Positive side of channel-1 TMDS low-voltage signal differential input pair Channel-1 receives green-pixel data in active display and CTL1 control signals in blank.
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TFP401 TFP401A SLDS120E – MARCH 2000 – REVISED JULY 2013 www.ti.com THERMAL INFORMATION (continued) TFP401, TFP401A THERMAL METRIC (1) PZP UNIT 100 PINS θJCtop Junction-to-case (top) thermal resistance 12.3 °C/W θJB Junction-to-board thermal resistance 7.3 °C/W ψJT Junction-to-top characterization parameter 0.3 °C/W ψJB Junction-to-board characterization parameter 7.2 °C/W θJCbot Junction-to-case (bottom) thermal resistance 1.
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TFP401 TFP401A www.ti.
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TFP401 TFP401A SLDS120E – MARCH 2000 – REVISED JULY 2013 www.ti.com AC ELECTRICAL CHARACTERISTICS (continued) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS 1 pixel/clock, PIXS = low, OCK_INV = high tsu2 fODCK 4 2 pixel and STAG, PIXS = high, STAG = low, OCK_INV = high 1.5 1 pixel/clock, PIXS = low, OCK_INV = high 0.5 2 pixel and STAG, PIXS = high, STAG = low, OCK_INV = high 2.4 2 pixel/clock, PIXS = high, STAG = high, OCK_INV = high 2.
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TFP401 TFP401A www.ti.com SLDS120E – MARCH 2000 – REVISED JULY 2013 PARAMETER MEASUREMENT INFORMATION tr1 QE[23:0], QO[23:0], DE, CTK[3:1], HSYNC, VSYNC tf1 80% 80% 20% 20% Figure 1. Rise and Fall Times of Data and Control Signals N N tr2 1/fODCK tf2 80% ODCK ODCK 80% 20% 20% Figure 2. Rise and Fall Times of ODCK N N Figure 3.
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TFP401 TFP401A SLDS120E – MARCH 2000 – REVISED JULY 2013 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) twL(PDL_MIN) VIH PD tp(PDH-V) PD VIL DFO, ST, PIXS, STAG, Rx[2:0]+, Rx[2:0]–, OCK_INV Figure 9. Delay From PD Low to High Before Inputs Are Active N N TX2 Figure 10. Minimum Time PD Low N N 50% TX1 tccs TX0 50% Figure 11. Analog Input Channel-to-Channel Skew N N tt(HSC) tt(FSC) DE SCDT Figure 12.
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TFP401 TFP401A www.ti.com SLDS120E – MARCH 2000 – REVISED JULY 2013 requires a TMDS-compatible receiver like the TI TFP401/401A to decode the serial bit stream back to the same 24-bit pixel data and control signals that originated at the host. This decoded data can then be applied directly to the flat-panel drive circuitry to produce an image on the display. Because the host and display can be separated by distances up to 5 meters or more, serial transmission of the pixel data is preferred.
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TFP401 TFP401A SLDS120E – MARCH 2000 – REVISED JULY 2013 www.ti.com TFP401/401A TMDS INPUT LEVELS AND INPUT IMPEDANCE MATCHING The TMDS inputs to the TFP401/401A receiver have a fixed single-ended termination to AVDD. The TFP401/401A is internally optimized using a laser trim process to precisely fix the impedance at 50 Ω. The device functions normally with or without a resistor on the EXT_RES pin, so it remains drop-in compatible with current sockets.
PAGE 13
TFP401 TFP401A www.ti.com SLDS120E – MARCH 2000 – REVISED JULY 2013 The TFP401A integrates HSYNC regeneration circuitry that provides a seamless interface to these noncompliant transmitters. The position of the data enable (DE) signal is always fixed in relation to data, irrespective of the location of HSYNC. The TFP401A receiver uses the DE and clock signals to recreate stable vertical and horizontal sync signals.
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TFP401 TFP401A SLDS120E – MARCH 2000 – REVISED JULY 2013 www.ti.com Drive Strength (ST = high for high drive strength, ST = low for low drive strength). The TFP401/401A allows for selectable output drive strength on the data, control, and ODCK outputs. See the DC Electrical Characteristics table for the values of IOH and IOL current drives for a given ST state. The high output drive strength offers approximately two times the drive as the low-output drive strength. Time-Staggered Pixel Output.
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TFP401 TFP401A www.ti.com SLDS120E – MARCH 2000 – REVISED JULY 2013 Table 1. TI 100-TQFP (14 mm × 14 mm × 1 mm) / 0.5-mm Lead Pitch PARAMETER Theta-JA (1) Theta-JC (2) (1) (2) Maximum power dissipation (1) (2) (3) (1) (2) (3) WITHOUT PowerPAD™ Package PowerPAD™ Package, NOT CONNECTED TO PCB THERMAL PLANE PowerPAD™ Package, CONNECTED TO PCB THERMAL PLANE (1) 45°C/W 27.3°C/W 17.3°C/W 3.11°C/W 0.12°C/W 0.12°C/W 1.6 W 2.7 W 4.3 W Specified with 2-oz. (0.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 31-May-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.