Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal TSSOP 32

THS1206

SLAS217H – MAY 1999 – REVISED JULY 2003#

12-BIT, 4 ANALOG INPUT, 6 MSPS, SIMULTANEOUS SAMPLINGANA-

LOG-TO-DIGITAL CONVERTERS

FEATURES

High-Speed 6 MSPS ADC

4 Analog Inputs

Simultaneous Sampling of 4 Single-Ended

Signals or 2 Differential Signals or

Combination of Both

Differential Nonlinearity Error: ±1 LSB

Integral Nonlinearity Error: ±1.5 LSB

Signal-to-Noise and Distortion Ratio: 68 dB

at f

= 2 MHz

Auto-Scan Mode for 2, 3, or 4 Inputs

3-V or 5-V Digital Interface Compatible

Low Power: 216 mW Max

5-V Analog Single Supply Operation

Internal Voltage References ...50 PPM/°C

and ±5% Accuracy

Glueless DSP Interface

Parallel µC/DSP Interface

Integrated FIFO

Available in TSSOP Package

Pin Compatible Upgrade to THS10064

APPLICATIONS

Radar Applications

Communications

Control Applications

High-Speed DSP Front-End

Automotive Applications

DESCRIPTION

The THS1206 is a CMOS, low-power, 12-bit, 6 MSPS

analog-to-digital converter (ADC). The speed, resolution,

bandwidth, and single-supply operation are suited for

applications in radar, imaging, high-speed acquisition, and

communications. A multistage pipelined architecture with

output error correction logic provides for no missing codes

over the full operating temperature range. Internal control

registers are used to program the ADC into the desired

mode. The THS1206 consists of four analog inputs, which

are sampled simultaneously. These inputs can be selected

individually and configured to single-ended or differential

inputs. An integrated 16 word deep FIFO allows the

storage of data in order to take the load off of the processor

connected to the ADC. Internal reference voltages for the

ADC (1.5 V and 3.5 V) are provided.

An external reference can also be chosen to suit the dc

accuracy and temperature drift requirements of the

application. Two different conversion modes can be

selected. In single conversion mode, a single and

simultaneous conversion of up to four inputs can be

initiated by using the single conversion start signal

(CONVST

). The conversion clock in single conversion

mode is generated internally using a clock oscillator

circuit. In continuous conversion mode, an external clock

signal is applied to the CONV_CLK input of the THS1206.

The internal clock oscillator is switched off in continuous

conversion mode.

The THS1206C is characterized for operation from 0°C to

70°C while the THS1206I is characterized for operation

from –40°C to 85°C. The THS1206Q is characterized to

meet the rigorous requirements of the automotive

environment from –40°C to 125°C. The THS1206M is

characterized for operation over the full military

temperature range of –55°C to 125°C.

PRODUCT PREVIEW information concerns products in the formative or design

phase of development. Characteristic data and other specifications are design

goals. Texas Instruments reserves the right to change or discontinue these

products without notice.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

www.ti.com

Summary of content (43 pages)

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THS1206 www.ti.com SLAS217H – MAY 1999 – REVISED JULY 2003# 12-BIT, 4 ANALOG INPUT, 6 MSPS, SIMULTANEOUS SAMPLINGANALOG-TO-DIGITAL CONVERTERS FEATURES D D D D D D D D D D D D D D D D High-Speed 6 MSPS ADC 4 Analog Inputs Simultaneous Sampling of 4 Single-Ended Signals or 2 Differential Signals or Combination of Both Differential Nonlinearity Error: ±1 LSB Integral Nonlinearity Error: ±1.
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THS1206 www.ti.com SLAS217H – MAY 1999 – REVISED JULY 2003# ORDERING INFORMATION PACKAGED DEVICE TA TSSOP (DA) 0°C to 70°C THS1206CDA –40°C to 85°C THS1206IDA –40°C to 125°C THS1206QDA –55°C to 125°C THS1206MDA These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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THS1206 www.ti.com SLAS217H – MAY 1999 – REVISED JULY 2003# RECOMMENDED OPERATING CONDITIONS POWER SUPPLY Supply voltage MIN NOM MAX AVDD DVDD 4.75 5 5.25 3 3.3 5.25 BVDD 3 3.3 5.25 ANALOG AND REFERENCE INPUTS MIN Analog input voltage in single-ended configuration MAX V 2.5 VREFP 4 3.5 AVDD–1.2 V External reference voltage,VREFP (optional) External reference voltage, VREFM (optional) 1.
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THS1206 www.ti.
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THS1206 www.ti.com SLAS217H – MAY 1999 – REVISED JULY 2003# ELECTRICAL CHARACTERISTICS over recommended operating conditions, VREF = internal, fx = 6 MHz, fI = 2 MHz at –1 dBFS (unless otherwise noted) AC SPECIFICATIONS, AVDD = 5 V, BVDD = DVDD = 3.
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THS1206 www.ti.
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THS1206 www.ti.com SLAS217H – MAY 1999 – REVISED JULY 2003# Terminal Functions TERMINAL I/O DESCRIPTION NAME NO.
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THS1206 www.ti.com SLAS217H – MAY 1999 – REVISED JULY 2003# FUNCTIONAL BLOCK DIAGRAM AVDD DVDD 2.5 V 3.5 V REFP 1.225 V REF 1.
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THS1206 www.ti.com SLAS217H – MAY 1999 – REVISED JULY 2003# TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION vs SAMPLING FREQUENCY (SINGLE-ENDED) SIGNAL-TO-NOISE AND DISTORTION vs SAMPLING FREQUENCY (SINGLE-ENDED) 70 SINAD – Signal-to-Noise and Distortion – dB THD – Total Harmonic Distortion – dB 80 75 70 65 60 55 50 AVDD = 5 V, DVDD = BVDD = 3 V, fIN = 500 kHz, AIN = –0.5 dB FS 45 40 AVDD = 5 V, DVDD = BVDD = 3 V, fIN = 500 kHz, AIN = –0.
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THS1206 www.ti.com SLAS217H – MAY 1999 – REVISED JULY 2003# TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION vs SAMPLING FREQUENCY (DIFFERENTIAL) SIGNAL-TO-NOISE AND DISTORTION vs SAMPLING FREQUENCY (DIFFERENTIAL) 85 SINAD – Signal-to-Noise and Distortion – dB 80 THD – Total Harmonic Distortion – dB 80 75 70 65 60 55 50 AVDD = 5 V, DVDD = BVDD = 3 V, fIN = 500 kHz, AIN = –0.5 dB FS 45 40 AVDD = 5 V, DVDD = BVDD = 3 V, fIN = 500 kHz, AIN = –0.
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THS1206 www.ti.com SLAS217H – MAY 1999 – REVISED JULY 2003# TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY (SINGLE-ENDED) SIGNAL-TO-NOISE AND DISTORTION vs INPUT FREQUENCY (SINGLE-ENDED) 80 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 6 MHz, AIN = –0.5 dB FS 80 SINAD – Signal-to-Noise and Distortion – dB THD – Total Harmonic Distortion – dB 85 75 70 65 60 55 50 45 40 0 0.5 1.0 1.5 2.0 2.5 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 6 MHz, AIN = –0.5 dB FS 75 70 65 60 55 50 45 40 3.
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THS1206 www.ti.com SLAS217H – MAY 1999 – REVISED JULY 2003# TYPICAL CHARACTERISTICS SIGNAL-TO-NOISE AND DISTORTION vs INPUT FREQUENCY (DIFFERENTIAL) TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY (DIFFERENTIAL) 80 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 6 MHz, AIN = –0.5 dB FS 80 SINAD – Signal-to-Noise and Distortion – dB THD – Total Harmonic Distortion – dB 90 70 60 50 40 30 20 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 6 MHz, AIN = –0.5 dB FS 70 60 50 40 30 20 0 0.5 1.0 1.5 2.0 2.5 3.0 3.
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THS1206 www.ti.com SLAS217H – MAY 1999 – REVISED JULY 2003# TYPICAL CHARACTERISTICS EFFECTIVE NUMBER OF BITS vs SAMPLING FREQUENCY (DIFFERENTIAL) EFFECTIVE NUMBER OF BITS vs SAMPLING FREQUENCY (SINGLE-ENDED) 12 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 6 MHz, AIN = –0.5 dB FS ENOB – Effective Number of Bits – Bits ENOB – Effective Number of Bits – Bits 12 11 10 9 8 7 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 6 MHz, AIN = –0.
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THS1206 www.ti.com SLAS217H – MAY 1999 – REVISED JULY 2003# TYPICAL CHARACTERISTICS GAIN vs INPUT FREQUENCY (SINGLE-ENDED) 5 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 6 MHz, AIN = –0.
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THS1206 www.ti.com SLAS217H – MAY 1999 – REVISED JULY 2003# TYPICAL CHARACTERISTICS FAST FOURIER TRANSFORM (4096 POINTS) (SINGLE-ENDED) vs FREQUENCY 20 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 6 MHz, AIN = –0.5 dB FS Magnitude – dB 0 –20 –40 –60 –80 –100 –120 –140 0 500000 1000000 1500000 2000000 2500000 3000000 3500000 f – Frequency – Hz Figure 22 FAST FOURIER TRANSFORM (4096 POINTS) (DIFFERENTIAL) vs FREQUENCY 20 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 6 MHz, AIN = –0.
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THS1206 www.ti.com SLAS217H – MAY 1999 – REVISED JULY 2003# DETAILED DESCRIPTION Reference Voltage The THS1206 has a built-in reference, which provides the reference voltages for the ADC. VREFP is set to 3.5 V and VREFM is set to 1.5 V. An external reference can also be used through two reference input pins, REFP and REFM, if the reference source is programmed as external.
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THS1206 www.ti.com SLAS217H – MAY 1999 – REVISED JULY 2003# Table 2 shows the maximum conversion rate in the single conversion mode. Table 2. Maximum Conversion Rate in Single Conversion Mode(1) NUMBER OF CHANNELS MAXIMUM CONVERSION RATE PER CHANNEL 1 single-ended channel 1 3 MSPS 2 single-ended channels 2 2 MSPS 3 single-ended channels 3 1.5 MSPS 4 single-ended channels 4 1.
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THS1206 www.ti.com SLAS217H – MAY 1999 – REVISED JULY 2003# CONTINUOUS CONVERSION MODE The internal clock oscillator used in the single-conversion mode is switched off in continuous conversion mode. In continuous conversion mode, (bit 1 of control register 0 set to 0) the ADC operates with a free running external clock signal CONV_CLK. With every rising edge of the CONV_CLK signal a new converted value is written into the FIFO.
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THS1206 www.ti.com SLAS217H – MAY 1999 – REVISED JULY 2003# Figure 27 shows the timing of continuous conversion mode when three analog input channels are selected. The maximum throughput rate per channel is 2 MSPS in this mode. The data flow in the bottom of the figure shows in which order the converted data is written into the FIFO. The timing of the DATA_AV signal shown here is for a trigger level set to 3.
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THS1206 www.ti.com SLAS217H – MAY 1999 – REVISED JULY 2003# DIGITAL OUTPUT DATA FORMAT The digital output data format of the THS1206 can either be in binary format or in twos complement format. The following tables list the digital outputs for the analog input voltages. Table 3. Binary Output Format for Single-Ended Configuration SINGLE-ENDED, BINARY OUTPUT ANALOG INPUT VOLTAGE DIGITAL OUTPUT CODE AIN = VREFP FFFh AIN = (VREFP + VREFM)/2 800h AIN = VREFM 000h Table 4.
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THS1206 www.ti.com SLAS217H – MAY 1999 – REVISED JULY 2003# FIFO DESCRIPTION In order to facilitate an efficient connection to today’s processors, the THS1206 is supplied with a FIFO. This integrated FIFO enables a problem-free processing of data with today’s processors. The FIFO is provided as a flexible circular buffer. The circular buffer integrated in the THS1206 can store up to 16 conversion values. Therefore, the amount of interrupts to be served by a processor can be reduced significantly.
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THS1206 www.ti.com SLAS217H – MAY 1999 – REVISED JULY 2003# READING DATA FROM THE FIFO The THS1206 informs the connected processor via the digital output DATA_AV (data available) that a block of conversion values are ready to be read. The block size to be read is always equal to the setting of the trigger level. The selectable trigger levels depend on the number of selected analog input channels. For example, when choosing one analog input, a trigger level of 1, 4, 8 and 14 can be selected.
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THS1206 www.ti.com SLAS217H – MAY 1999 – REVISED JULY 2003# ADC CONTROL REGISTER The THS1206 contains two 10-bit wide control registers (CR0, CR1) in order to program the device into the desired mode. The bit definitions of both control registers are shown in Table 7. Table 7.
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THS1206 www.ti.com SLAS217H – MAY 1999 – REVISED JULY 2003# INITIALIZATION OF THE THS1206 The initialization of the THS1206 should be done according to the configuration flow shown in Figure 34.
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THS1206 www.ti.com SLAS217H – MAY 1999 – REVISED JULY 2003# ADC CONTROL REGISTERS Control Register 0 (see Table 8) BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 0 TEST1 TEST0 SCAN DIFF1 DIFF0 CHSEL1 CHSEL0 PD MODE VREF Table 9.
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THS1206 www.ti.com SLAS217H – MAY 1999 – REVISED JULY 2003# ANALOG INPUT CHANNEL SELECTION The analog input channels of the THS1206 can be selected via bits 3 to 7 of control register 0. One single channel (single-ended or differential) is selected via bit 3 and bit 4 of control register 0. Bit 5 controls the selection between single-ended and differential configuration. Bit 6 and bit 7 select the autoscan mode, if more than one input channel is selected. Table 10 shows the possible selections.
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THS1206 www.ti.com SLAS217H – MAY 1999 – REVISED JULY 2003# Control Register 1 (see Table 8) BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 1 RBACK OFFSET BIN/2s R/W DATA_P DATA_T TRIG1 TRIG0 OVFL/FRST RESET Table 12. Control Register 1 Bit Functions BITS RESET VALUE NAME 0 0 RESET FUNCTION Reset Writing a 1 into this bit resets the device and sets the control register 0 and control register 1 to the reset values.
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THS1206 www.ti.com SLAS217H – MAY 1999 – REVISED JULY 2003# FIFO TRIGGER LEVEL Bit 2 and bit 3 (TRIG1, TRIG0) of control register 1 are used to set the trigger level of the FIFO (see Table 13). If the trigger level is reached, the DATA_AV (data available) signal becomes active according to the setting of the signal DATA_AV to indicate to the processor that the ADC values can be read. Table 13 shows four different programmable trigger levels for each configuration.
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THS1206 www.ti.com SLAS217H – MAY 1999 – REVISED JULY 2003# DATA_AV TYPE Bit 4 and bit 5 (DATA_T, DATA_P) of control register 1 are used to program the signal DATA_AV. Bit 4 of control register 1 determines whether the DATA_AV signal is static or a pulse. Bit 5 of the control register determines the polarity of DATA_AV. This is shown in Table 14. Table 14.
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THS1206 www.ti.com SLAS217H – MAY 1999 – REVISED JULY 2003# TIMING AND SIGNAL DESCRIPTION OF THE THS1206 Read Timing (using R/W, CS0-controlled) Figure 36 shows the read-timing behavior when the WR(R/W) input is programmed as a combined read-write input R/W. The RD input has to be tied to high-level in this configuration. This timing is called CS0-controlled because CS0 is the last external signal of CS0, CS1, and R/W, which becomes valid.
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THS1206 www.ti.com SLAS217H – MAY 1999 – REVISED JULY 2003# Write Timing (using R/W, CS0-controlled) Figure 37 shows the write-timing behavior when the WR(R/W) input is programmed as a combined read-write input R/W. The RD input has to be tied to high-level in this configuration. This timing is called CS0-controlled because CS0 is the last external signal of CS0, CS1, and R/W, which becomes valid.
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THS1206 www.ti.com SLAS217H – MAY 1999 – REVISED JULY 2003# INTERFACING THE THS1206 TO THE TMS320C54X USING I/O STROBE The following application circuit shows an interface of the THS1206 to the TMS320C54x. The read and write timings (using R/W, CS0-controlled) shown before are valid for this specific interface.
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THS1206 www.ti.com SLAS217H – MAY 1999 – REVISED JULY 2003# Write Timing (using WR, WR-controlled) Figure 39 shows the write-timing behavior when the WR(R/W) input is programmed as a write input WR only. The input RD acts as the read input in this configuration. This timing is called WR-controlled because WR is the last external signal of CS0, CS1, and WR, which becomes valid.
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THS1206 www.ti.com SLAS217H – MAY 1999 – REVISED JULY 2003# INTERFACING THE THS1206 TO THE TMS320C6201 DSP The following application circuit shows an interface of the THS1206 to the TMS320C6201. The read (using RD, RD-controlled) and write timings (using WR, WR-controlled) shown before are valid for this specific interface.
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THS1206 www.ti.com SLAS217H – MAY 1999 – REVISED JULY 2003# A differential operation is desired for many applications. Figure 41 shows a simplified model for the analog inputs AINM and AINP, which are configured for differential operation. This configuration has a few advantages, which are discussed in the following paragraphs. VREFP AINP + Σ VADC 12-Bit ADC – AINM VREFM Figure 41.
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THS1206 www.ti.com SLAS217H – MAY 1999 – REVISED JULY 2003# DC COUPLING An operational amplifier can be configured to shift the signal level according to the analog input voltage range of the THS1206. The analog input voltage range of the THS1206 goes from 1.5 V to 3.5 V. An op-amp specified for 5-V single supply can be used as shown in Figure 42.
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THS1206 www.ti.com SLAS217H – MAY 1999 – REVISED JULY 2003# DEFINITIONS OF SPECIFICATIONS AND TERMINOLOGY Integral Nonlinearity Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale. The point used as zero occurs 1/2 LSB before the first code transition. The full-scale point is defined as level 1/2 LSB beyond the last code transition.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com (3) 11-Apr-2013 MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
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PACKAGE MATERIALS INFORMATION www.ti.com 18-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device THS1206IDAR Package Package Pins Type Drawing TSSOP DA 32 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 24.4 Pack Materials-Page 1 8.6 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 11.5 1.6 12.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 18-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) THS1206IDAR TSSOP DA 32 2000 367.0 367.0 45.
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