Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - AD converter (ADC) External , Internal TSSOP 32



SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002

       

 

FEATURES

D Simultaneous Sampling of 4 Single-Ended

Signals or 2 Differential Signals or

Combination of Both

D Signal-to-Noise and Distortion Ratio:

68 dB at f

= 2 MHz

D Differential Nonlinearity Error: ±1 LSB

D Integral Nonlinearity Error: ±1.5 LSB

D Auto-Scan Mode for 2, 3, or 4 Inputs

D 3-V or 5-V Digital Interface Compatible

D Low Power: 216 mW Max at 5 V

D Power Down: 1 mW Max

D 5-V Analog Single Supply Operation

D Internal Voltage References ...50 PPM/°C

and ±5% Accuracy

D Glueless DSP Interface

D Parallel µC/DSP Interface

APPLICATIONS

D Radar Applications

D Communications

D Control Applications

D High-Speed DSP Front-End

D Automotive Applications

DESCRIPTION

The THS1207 is a CMOS, low-power, 12-bit, 6 MSPS

analog-to-digital converter (ADC). The speed,

resolution, bandwidth, and single-supply operation are

suited for applications in radar, imaging, high-speed

acquisition, and communications. A multistage

pipelined architecture with output error correction logic

provides for no missing codes over the full operating

temperature range. Internal control registers are used

to program the ADC into the desired mode. The

THS1207 consists of four analog inputs, which are

sampled simultaneously. These inputs can be selected

individually and configured to single-ended or

differential-inputs. Internal reference voltages for the

ADC (1.5 V and 3.5 V) are provided. An external

reference can also be chosen to suit the dc accuracy

and temperature drift requirements of the application.

The THS1207C is characterized for operation from 0°C

to 70°C, the THS1207I is characterized for operation

from –40°C to 85°C.

BGND

D10/RA0

D11/RA1

CONV_CLK

SYNC

AINP

AINM

BINP

BINM

REFIN

REFOUT

REFP

REFM

AGND

CS0

CS1

(R/W)

DGND

DA PACKAGE

(TOP VIEW)

ORDERING INFORMATION

PACKAGED DEVICE

TSSOP

(DA)

0°C to 70°C THS1207CDA

–40°C to 85°C THS1207IDA

         

          

         

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments

semiconductor products and disclaimers thereto appears at the end of this data sheet.

www.ti.com

Summary of content (32 pages)

PAGE 1
www.ti.com SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002 FEATURES D Simultaneous Sampling of 4 Single-Ended Signals or 2 Differential Signals or Combination of Both D Signal-to-Noise and Distortion Ratio: D D D D D D D D 68 dB at fI = 2 MHz Differential Nonlinearity Error: ±1 LSB Integral Nonlinearity Error: ±1.5 LSB Auto-Scan Mode for 2, 3, or 4 Inputs to program the ADC into the desired mode.
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www.ti.com SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted(1) UNITS Supply Su ly voltage range DGND to DVDD –0.3 V to 6.5 V BGND to BVDD –0.3 V to 6.5 V AGND to AVDD –0.3 V to 6.
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www.ti.com SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002 ELECTRICAL CHARACTERISTICS over recommended operating conditions, AVDD = DVDD = 5 V, BVDD = 3.
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www.ti.com SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002 ELECTRICAL CHARACTERISTICS over recommended operating conditions, VREF = internal, fs = 6 MSPS, fI = 2 MHz at –1 dBFS (unless otherwise noted) AC SPECIFICATIONS, AVDD = DVDD = 5 V, BVDD = 3.
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www.ti.com SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002 Terminal Functions TERMINAL NAME NO.
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www.ti.com SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002 FUNCTIONAL BLOCK DIAGRAM AVDD DVDD 2.5 V 3.5 V REFP VREFP 1.225 V REF 1.
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www.ti.com SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002 TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION vs SAMPLING FREQUENCY (SINGLE-ENDED) SIGNAL-TO-NOISE AND DISTORTION vs SAMPLING FREQUENCY (SINGLE-ENDED) 80 SINAD – Signal-to-Noise and Distortion – dB 70 THD – Total Harmonic Distortion – dB 75 70 65 60 55 50 AVDD = 5 V, DVDD = BVDD = 3 V, fIN = 500 kHz, AIN = –0.5 dB FS 45 40 AVDD = 5 V, DVDD = BVDD = 3 V, fIN = 500 kHz, AIN = –0.
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www.ti.com SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002 TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION vs SAMPLING FREQUENCY (DIFFERENTIAL) SIGNAL-TO-NOISE AND DISTORTION vs SAMPLING FREQUENCY (DIFFERENTIAL) 85 SINAD – Signal-to-Noise and Distortion – dB 80 THD – Total Harmonic Distortion – dB 80 75 70 65 60 55 50 AVDD = 5 V, DVDD = BVDD = 3 V, fIN = 500 kHz, AIN = –0.5 dB FS 45 40 AVDD = 5 V, DVDD = BVDD = 3 V, fIN = 500 kHz, AIN = –0.
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www.ti.com SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002 TYPICAL CHARACTERISTICS TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY (SINGLE-ENDED) SIGNAL-TO-NOISE AND DISTORTION vs INPUT FREQUENCY (SINGLE-ENDED) 80 80 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 6 MHz, AIN = –0.5 dB FS SINAD – Signal-to-Noise and Distortion – dB THD – Total Harmonic Distortion – dB 85 75 70 65 60 55 50 45 40 0.0 0.5 1.0 1.5 2.0 2.5 75 70 65 60 55 50 45 40 0.0 3.
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www.ti.com SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002 TYPICAL CHARACTERISTICS SIGNAL-TO-NOISE AND DISTORTION vs INPUT FREQUENCY (DIFFERENTIAL) TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY (DIFFERENTIAL) 80 80 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 6 MHz, AIN = –0.5 dB FS SINAD – Signal-to-Noise and Distortion – dB THD – Total Harmonic Distortion – dB 90 70 60 50 40 30 20 0.0 0.5 1.0 1.5 2.0 2.5 3.0 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 6 MHz, AIN = –0.
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www.ti.com SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002 TYPICAL CHARACTERISTICS EFFECTIVE NUMBER OF BITS vs SAMPLING FREQUENCY (SINGLE-ENDED) EFFECTIVE NUMBER OF BITS vs SAMPLING FREQUENCY (DIFFERENTIAL) 12 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 6 MHz, AIN = –0.5 dB FS ENOB – Effective Number of Bits – Bits ENOB – Effective Number of Bits – Bits 12 11 10 9 8 7 6 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 6 MHz, AIN = –0.
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www.ti.com SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002 TYPICAL CHARACTERISTICS GAIN vs INPUT FREQUENCY (SINGLE-ENDED) 5 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 6 MHz, AIN = –0.5 dB FS 0 G – Gain – dB –5 –10 –15 –20 –25 –30 0 10 20 30 40 50 60 70 80 90 100 110 120 fi – Input Frequency – MHz Figure 21 FAST FOURIER TRANSFORM (4096 POINTS) (SINGLE-ENDED) vs FREQUENCY 20 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 6 MHz, AIN = –0.
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www.ti.com SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002 TYPICAL CHARACTERISTICS FAST FOURIER TRANSFORM (4096 POINTS) (DIFFERENTIAL) vs FREQUENCY 20 AVDD = 5 V, DVDD = BVDD = 3 V, fs = 6 MHz, AIN = –0.5 dB FS Magnitude – dB 0 –20 –40 –60 –80 –100 –120 –140 0 500000 1000000 1500000 2000000 2500000 3000000 3500000 f – Frequency – Hz DNL – Differential Nonlinearity – LSB Figure 23 DIFFERENTIAL NONLINEARITY vs ADC CODE 1.0 0.8 AVDD = 5 V DVDD = BVDD = 3 V fs = 8 MSPS 0.6 0.4 0.2 –0.
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www.ti.com SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002 DETAILED DESCRIPTION Reference Voltage The THS1207 has a built-in reference, which provides the reference voltages for the ADC. VREFP is set to 3.5 V and VREFM is set to 1.5 V. An external reference can also be used through two reference input pins, REFP and REFM, if the reference source is programmed as external.
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www.ti.com SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002 To provide the system with channel information, the THS1207 utilizes an active low SYNC signal. When operated in a multichannel configuration, the SYNC signal is active low when data from channel one is available to the databus. When operated in single-channel mode (single-ended or differential operation) the SYNC signal is disabled. Figure 26 shows the timing of the conversion when one analog input channel is selected.
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www.ti.com SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002 Figure 28 shows the conversion timing when 3 analog input channels are selected. The maximum throughput rate per channel is 2 MSPS in this mode. The data flow in the bottom of the figure shows in which order the converted data is available to the databus. The signal SYNC is always active low if data of channel one is available to the databus.
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www.ti.com SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002 DIGITAL OUTPUT DATA FORMAT The digital output data format of the THS1207 can either be in binary format or in twos complement format. The following tables list the digital outputs for the analog input voltages. Table 2. Binary Output Format for Single-Ended Configuration SINGLE-ENDED, BINARY OUTPUT ANALOG INPUT VOLTAGE DIGITAL OUTPUT CODE AIN = VREFP FFFh AIN = (VREFP + VREFM)/2 800h AIN = VREFM 000h Table 3.
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www.ti.com SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002 ADC CONTROL REGISTER The THS1207 contains two 10-bit wide control registers (CR0, CR1) in order to program the device into the desired mode. The bit definitions of both control registers are shown in Table 6. Table 6.
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www.ti.com SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002 Control Register 0 (see Table 7) BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 0 TEST1 TEST0 SCAN DIFF1 DIFF0 CHSEL1 CHSEL0 PD RESERVED VREF Table 8. Control Register 0 Bit Functions BITS RESET VALUE NAME 0 0 VREF 1 0 RESERVED 2 0 PD 3, 4 0,0 CHSEL0, CHSEL1 5,6 1,0 DIFF0, DIFF1 7 0 SCAN Autoscan enable Bit 7 enables or disables the autoscan function of the ADC.
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www.ti.com SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002 ANALOG INPUT CHANNEL SELECTION The analog input channels of the THS1207 can be selected via bits 3 to 7 of control register 0. One channel (single-ended or differential) is selected via bit 3 and bit 4 of control register 0. Bit 5 controls the selection between single-ended and differential configuration. Bit 6 and bit 7 select the autoscan mode, if more than one input channel is selected. Table 9 shows the possible selections. Table 9.
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www.ti.com SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002 Control Register 1 (see Table 7) BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 0 1 RBACK OFFSET BIN/2s R/W RESERVED RESERVED RESERVED RESERVED SRST RESET Table 11. Control Register 1 Bit Functions BITS RESET VALUE NAME 0 0 RESET FUNCTION Reset Writing a 1 into this bit resets the device and sets the control register 0 and control register 1 to the reset values.
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www.ti.com SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002 TIMING AND SIGNAL DESCRIPTION OF THE THS1207 The reading from the THS1207 and writing to the THS1207 is performed by using the chip select inputs (CS0, CS1), the write input WR and the read input RD. The write input is configurable to a combined read/write input (R/W). This is desired in cases where the connected processor consists of a combined read/write output signal (R/W).
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www.ti.com SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002 Read Timing (using RD, RD-controlled) Figure 32 shows the read-timing behavior when the WR(R/W) input is programmed as a write-input only. The input RD acts as the read-input in this configuration. This timing is called RD-controlled because RD is the last external signal of CS0, CS1, and RD which becomes valid. CS0 CS1 WR tsu(CS) ÓÓÓÓ ÓÓÓÓ th(CS) tw(RD) 10% RD ÔÔÔ ÔÔÔ 10% ta th 90% 90% D(0–9) td(CSDAV) 90% DATA_AV Figure 32.
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www.ti.com SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002 Write Timing (using WR, WR-controlled) Figure 33 shows the write-timing behavior when the WR(R/W) input is programmed as a write input WR only. The input RD acts as the read input in this configuration. This timing is called WR-controlled because WR is the last external signal of CS0, CS1, and WR which becomes valid.
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www.ti.com SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002 Read Timing (using R/W, CS0-controlled) Figure 34 shows the read-timing behavior when the WR(R/W) input is programmed as a combined read-write input R/W. The RD input has to be tied to high-level in this configuration. This timing is called CS0-controlled because CS0 is the last external signal of CS0, CS1, and R/W which becomes valid.
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www.ti.com SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002 Write Timing Diagram (using R/W, CS0-controlled) Figure 35 shows the write-timing behavior when the WR(R/W) input is programmed as a combined read-write input R/W. The RD input has to be tied to high-level in this configuration. This timing is called CS0-controlled because CS0 is the last external signal of CS0, CS1, and R/W which becomes valid.
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www.ti.com SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002 ANALOG INPUT CONFIGURATION AND REFERENCE VOLTAGE The THS1207 features four analog input channels. These can be configured for either single-ended or differential operation. Figure 36 shows a simplified model, where a single-ended configuration for channel AINP is selected. The reference voltages for the ADC itself are VREFP and VREFM (either internal or external reference voltages). The analog input voltage range is between VREFM to VREFP.
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www.ti.com SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002 SINGLE-ENDED MODE OF OPERATION The THS1207 can be configured for single-ended operation using dc or ac-coupling. In either case, the input of the THS1207 must be driven from an operational amplifier that does not degrade the ADC performance. Because the THS1207 operates from a single supply 5 V, it is necessary to level-shift ground-based bipolar signals to comply with its input requirements. This can be achieved with dc and ac-coupling.
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www.ti.com SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002 DEFINITIONS OF SPECIFICATIONS AND TERMINOLOGY Integral Nonlinearity Integral nonlinearity refers to the deviation of each individual code from a line drawn from zero through full scale. The point used as zero occurs 1/2 LSB before the first code transition. The full-scale point is defined as level 1/2 LSB beyond the last code transition.
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PACKAGE OPTION ADDENDUM www.ti.
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