Datasheet


SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002
www.ti.com
22
TIMING AND SIGNAL DESCRIPTION OF THE THS1207
The reading from the THS1207 and writing to the THS1207 is performed by using the chip select inputs (CS0,
CS1), the write input WR and the read input RD. The write input is configurable to a combined read/write input
(R/W). This is desired in cases where the connected processor consists of a combined read/write output signal
(R/W). The two chip select inputs can be used to interface easily to a processor.
Reading from the THS1207 takes place by an internal RD
int
signal, which is generated from the logical
combination of the external signals CS0, CS1 and RD (see Figure 6). This signal is then used to strobe out the
words and to enable the output buffers. The last external signal (either CS0, CS1 or RD) to become valid makes
RD
int
active while the write input (WR) is inactive. The first of those external signals switching to an inactive
state deactivates RD
int
again.
Writing to the THS1207 takes place by an internal WR
int
signal, which is generated from the logical combination
of the external signals CS0, CS1 and WR. This signal strobes the control words into the control registers 0 and
1. The last external signal (either CS0, CS1 or WR) to become valid switches WR
int
active while the read input
(RD) is inactive. The first of those external signals going to its inactive state deactivates WR
int
again.
Read Enable
Write Enable
Control/Data
Registers
CS0
CS1
RD
WR
Data Bits
Figure 31. Logical Combination of CS0, CS1, RD, and WR