Datasheet

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SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002
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25
Read Timing (using R/W, CS0-controlled)
Figure 34 shows the read-timing behavior when the WR
(R/W) input is programmed as a combined read-write
input R/W. The RD input has to be tied to high-level in this configuration. This timing is called CS0-controlled
because CS0 is the last external signal of CS0, CS1, and R/W which becomes valid. The reading of the data
must be done with a certain timing relative to the conversion clock CONV_CLK, as illustrated in Figure 34.
t
su(CONV_CLKL–CS0L)
t
su(CS0H–CONV_CLKL)
t
a
t
h
10%
10%
90%
90%
90%
90%
90%
10%
10%
CONV_CLK
CS0
CS1
R/W
RD
D(O–11)
t
w(CS)
t
su(R/W)
t
h(R/W)
Figure 34. Read Timing Diagram Using R/W (CS0-controlled)
Read Timing Parameter (CS0-controlled)
PARAMETER MIN TYP MAX UNIT
t
su(CONV_CLKL-CSOL)
Setup time, CONV_CLK low before CS valid 10 ns
t
su(CSOH-CONV_CLKL)
Setup time, CS invalid to CONV_CLK low 20 ns
t
su(R/W)
Setup time, R/W high to last CS valid 0 ns
t
a
Access time, last CS valid to data valid 0 10 ns
t
h
Hold time, first CS invalid to data invalid 0 5 ns
t
h(R/W)
Hold time, first external CS invalid to R/W change 5 ns
t
w(CS)
Pulse duration, CS active 10 ns