Datasheet
SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002
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27
ANALOG INPUT CONFIGURATION AND REFERENCE VOLTAGE
The THS1207 features four analog input channels. These can be configured for either single-ended or
differential operation. Figure 36 shows a simplified model, where a single-ended configuration for channel AINP
is selected. The reference voltages for the ADC itself are V
REFP
and V
REFM
(either internal or external reference
voltages). The analog input voltage range is between V
REFM
to V
REFP
. This means that V
REFM
defines the
minimum voltage, and V
REFP
defines the maximum voltage, which can be applied to the ADC. The internal
reference source provides the voltage V
REFM
of 1.5 V and the voltage V
REFP
of 3.5 V (see also section
reference voltage). The resulting analog input voltage swing of 2 V can be expressed by:
V
REFM
v AINP v V
REFP
12-Bit
ADC
V
REFP
V
REFM
AINP
Figure 36. Single-Ended Input Stage
A differential operation is desired in many applications due to a better signal-to-noise ration. Figure 37 shows
a simplified model for the analog inputs AINM and AINP, which are configured for differential operation. The
differential operation mode provides in terms of performance benefits over single-ended mode and is therefore
recommended for best performance. The THS1207 offers 2 differential analog inputs and in the single-ended
mode 4 analog inputs. If the analog input architecture is differential, common mode noise and common mode
voltages can be rejected. Additional details for both modes are given below.
12-Bit
ADC
V
REFP
V
REFM
AINP
Σ
V
ADC
AINM
+
–
Figure 37. Differential Input Stage
In comparison to the single-ended configuration it can be seen that the voltage, V
ADC
, which is applied at the
input of the ADC is the difference between the input AINP and AINM. The voltage V
ADC
can be calculated as
follows:
V
ADC
+ ABS
(
AINP–AINM
)
The advantage to single-ended operation is that the common-mode voltage
V
CM
+
AINM ) AINP
2
can be rejected in the differential configuration, if the following condition for the analog input voltages is true:
AGND v AINM, AINP v AV
DD
1Vv V
CM
v 4V
(1)
(2)
(3)
(4)
(5)