Datasheet

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SLAS284A – AUGUST 2000 – REVISED DECEMBER 2002
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4
ELECTRICAL CHARACTERISTICS
over recommended operating conditions, V
REF
= internal, f
s
= 6 MSPS, f
I
= 2 MHz at –1 dBFS (unless otherwise noted)
AC SPECIFICATIONS, AV
DD
= DV
DD
= 5 V, BV
DD
= 3.3 V, C
L
< 30 pF
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SINAD
Signal to noise ratio + distortion
Differential mode 63 63
dB
SINAD Signal-to-noise ratio + distortion
Single-ended mode 62 64
dB
SNR
Signal to noise ratio
Differential mode 64 69
dB
SNR Signal-to-noise ratio
Single-ended mode 64 68
dB
THD
Total harmonic distortion
Differential mode –70 –67
dB
THD Total harmonic distortion
Single-ended mode –68 –64
dB
ENOB
Effective number of bits
Differential mode 10.17 10.5
Bits
ENOB Effective number of bits
Single-ended mode 10 10.3
Bits
SFDR
S
p
urious free dynamic range
Differential mode 67 71
dB
SFDR Spurious free dynamic range
Single-ended mode 65 69
dB
Analog Input
Full-power bandwidth with a source impedance of 150 Ω in
differential configuration.
Full scale sinewave 3dB
96
MHz
Full-power bandwidth with a source impedance of 150 Ω in
single-ended configuration.
Full scale sinewave, –3 dB
54
MHz
Small-signal bandwidth with a source impedance of 150 Ω in
differential configuration.
100 mV
pp
sinewave 3dB
96
MHz
Small-signal bandwidth with a source impedance of 150 Ω in
single-ended configuration.
100 mVpp sinewave, –3 dB
54
MHz
TIMING REQUIREMENTS
AV
DD
= DV
DD
= 5 V, BV
DD
= 3.3 V, V
REF
= internal, C
L
< 30 pF
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
pipe
Latency 5
CONV
CLK
t
su(CONV_CLKL-READL)
Setup time, CONV_CLK low before CS valid 10 ns
t
su(READH-CONV_CLKL)
Setup time, CS invalid to CONV_CLK low 20 ns
t
d(CONV_CLKL-SYNCL)
Delay time, CONV_CLK low to SYNC low 10 ns
t
d(CONV_CLKL-SYNCH)
Delay time, CONV_CLK low to SYNC high 10 ns